5 December 2011 A co-design method for parallel image processing accelerator based on DSP and FPGA
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Proceedings Volume 8005, MIPPR 2011: Parallel Processing of Images and Optimization and Medical Imaging Processing; 800506 (2011) https://doi.org/10.1117/12.901244
Event: Seventh International Symposium on Multispectral Image Processing and Pattern Recognition (MIPPR2011), 2011, Guilin, China
Abstract
In this paper, we present a co-design method for parallel image processing accelerator based on DSP and FPGA. DSP is used as application and operation subsystem to execute the complex operations, and in which the algorithms are resolving into commands. FPGA is used as co-processing subsystem for regular data-parallel processing, and operation commands and image data are transmitted to FPGA for processing acceleration. A series of experiments have been carried out, and up to a half or three quarter time is saved which supports that the proposed accelerator will consume less time and get better performance than the traditional systems.
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Ze Wang, Ze Wang, Kaijian Weng, Kaijian Weng, Zhao Cheng, Zhao Cheng, Luxin Yan, Luxin Yan, Jing Guan, Jing Guan, } "A co-design method for parallel image processing accelerator based on DSP and FPGA", Proc. SPIE 8005, MIPPR 2011: Parallel Processing of Images and Optimization and Medical Imaging Processing, 800506 (5 December 2011); doi: 10.1117/12.901244; https://doi.org/10.1117/12.901244
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