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8 July 2011 Parallel of low-level computer vision algorithms on a multi-DSP system
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Proceedings Volume 8009, Third International Conference on Digital Image Processing (ICDIP 2011); 800918 (2011) https://doi.org/10.1117/12.896265
Event: 3rd International Conference on Digital Image Processing, 2011, Chengdu, China
Abstract
Parallel hardware becomes a commonly used approach to satisfy the intensive computation demands of computer vision systems. A multiprocessor architecture based on hypercube interconnecting digital signal processors (DSPs) is described to exploit the temporal and spatial parallelism. This paper presents a parallel implementation of low level vision algorithms designed on multi-DSP system. The convolution operation has been parallelized by using redundant boundary partitioning. Performance of the parallel convolution operation is investigated by varying the image size, mask size and the number of processors. Experimental results show that the speedup is close to the ideal value. However, it can be found that the loading imbalance of processor can significantly affect the computation time and speedup of the multi- DSP system.
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Huaida Liu, Pingui Jia, Lijian Li, and Yiping Yang "Parallel of low-level computer vision algorithms on a multi-DSP system", Proc. SPIE 8009, Third International Conference on Digital Image Processing (ICDIP 2011), 800918 (8 July 2011); https://doi.org/10.1117/12.896265
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