This paper describes an approach for accurately simulating the reset noise of CTIA-based pixels. Using a circuit
simulator to find the reset noise of a CTIA based pixel is not straightforward, due to the noise sampling and charge redistribution
after the reset switch opens. This often leads to an equation-based analysis of the pixel noise, which is
cumbersome for actual design work and incompatible with a mixed-signal design flow for advanced ROIC designs.
In a CTIA-based ROIC, the start of pixel integration is defined by the opening of the CTIA reset switch. The opening of
this switch down-converts the wideband noise of the circuit to DC, and the charge is then redistributed by the CTIA to
create an output reset noise. This reset noise can be removed by correlated double sampling (CDS). However, it is
important to understand the magnitude of the reset noise in order to evaluate the effectiveness of the CDS scheme. CDS
can be performed either in the pixel, or externally in the analog or digital domains. The specifications of the signal chain
depend on the amount of reset noise and the degree of cancellation required.
Simulation of the reset noise in SPICE is not straightforward, since the charge is redistributed after the switch opens, and
the noise on the two capacitors is correlated and cannot be treated independently. We describe a simulation technique
that gives accurate estimates of the pixel reset noise, and verify the results using Spectre-RF.