Video compression algorithms such as H.264 offer much potential for parallel processing that is not always exploited by
the technology of a particular implementation. Consumer mobile encoding devices often achieve real-time performance
and low power consumption through parallel processing in Application Specific Integrated Circuit (ASIC) technology,
but many other applications require a software-defined encoder. High quality compression features needed for some
applications such as 10-bit sample depth or 4:2:2 chroma format often go beyond the capability of a typical consumer
electronics device. An application may also need to efficiently combine compression with other functions such as noise
reduction, image stabilization, real time clocks, GPS data, mission/ESD/user data or software-defined radio in a low
power, field upgradable implementation.
Low power, software-defined encoders may be implemented using a massively parallel memory-network processor array
with 100 or more cores and distributed memory. The large number of processor elements allow the silicon device to
operate more efficiently than conventional DSP or CPU technology. A dataflow programming methodology may be
used to express all of the encoding processes including motion compensation, transform and quantization, and entropy
coding. This is a declarative programming model in which the parallelism of the compression algorithm is expressed as
a hierarchical graph of tasks with message communication. Data parallel and task parallel design patterns are supported
without the need for explicit global synchronization control.
An example is described of an H.264 encoder developed for a commercially available, massively parallel memorynetwork