A new design methodology for parallel and distributed embedded systems is presented using the behavioural hardware
compiler ConPro providing an imperative programming model based on concurrently communicating sequential processes
(CSP) with an extensive set of interprocess-communication primitives and guarded atomic actions. The programming
language and the compiler-based synthesis process enables the design of constrained power- and resourceaware
embedded systems with pure Register-Transfer-Logic (RTL) efficiently mapped to FPGA and ASIC technologies.
Concurrency is modelled explicitly on control- and datapath level. Additionally, concurrency on data-path level
can be automatically explored and optimized by different schedulers.
The CSP programming model can be synthesized to hardware (SoC) and software (C,ML) models and targets. A common
source for both hardware and software implementation with identical functional behaviour is used.
Processes and objects of the entire design can be distributed on different hardware and software platforms, for example,
several FPGA components and software executed on several microprocessors, providing a parallel and distributed system.
Intersystem-, interprocess-, and object communication is automatically implemented with serial links, not visible
on programming level.
The presented design methodology has the benefit of high modularity, freedom of choice of target technologies, and
system architecture. Algorithms can be well matched to and distributed on different suitable execution platforms and
implementation technologies, using a unique programming model, providing a balance of concurrency and resource
An extended case study of a communication protocol used in high-density sensor-actuator networks should demonstrate
and compare the design of a hardware and software target. The communication protocol is suited for high-density intra-and