3 May 2011 Area-delay trade-offs of texture decompressors for a graphics processing unit
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Proceedings Volume 8067, VLSI Circuits and Systems V; 80670N (2011); doi: 10.1117/12.886929
Event: SPIE Microtechnologies, 2011, Prague, Czech Republic
Abstract
Graphics Processing Units have become a booster for the microelectronics industry. However, due to intellectual property issues, there is a serious lack of information on implementation details of the hardware architecture that is behind GPUs. For instance, the way texture is handled and decompressed in a GPU to reduce bandwidth usage has never been dealt with in depth from a hardware point of view. This work addresses a comparative study on the hardware implementation of different texture decompression algorithms for both conventional (PCs and video game consoles) and mobile platforms. Circuit synthesis is performed targeting both a reconfigurable hardware platform and a 90nm standard cell library. Area-delay trade-offs have been extensively analyzed, which allows us to compare the complexity of decompressors and thus determine suitability of algorithms for systems with limited hardware resources.
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Emilio Novoa Súñer, Pablo Ituero, Marisa López-Vallejo, "Area-delay trade-offs of texture decompressors for a graphics processing unit", Proc. SPIE 8067, VLSI Circuits and Systems V, 80670N (3 May 2011); doi: 10.1117/12.886929; https://doi.org/10.1117/12.886929
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KEYWORDS
Visualization

Field programmable gate arrays

Transparency

Detection and tracking algorithms

Graphics processing units

Video

Video acceleration

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