Self-repairing SRAM architecture to mitigate the inter-die process variations at 65nm technology

Sumit Kansal; Marco Lanuzza; Pasquale Corsonello

doi:10.1117/12.886873

3 May 2011 Self-repairing SRAM architecture to mitigate the inter-die process variations at 65nm technology

Sumit Kansal, Marco Lanuzza, Pasquale Corsonello

Proceedings Volume 8067, VLSI Circuits and Systems V; 80670X (2011) https://doi.org/10.1117/12.886873
Event: SPIE Microtechnologies, 2011, Prague, Czech Republic

Abstract

With aggressive scaling, one of the major barriers that CMOS technology faces is the increasing process variations. The variations in process parameters not only affect the performance of the devices but also degrade the parametric yield of the circuits. Adaptive repairing techniques like adaptive body bias were proved to be effective to mitigate variations in the process parameters. In this paper, we evaluate the use of zone based self-repairing techniques to mitigate the impact of process variations on SRAM cells. Two different techniques were experimented and analyzed through extensive Monte Carlo simulations and exploiting a commercial 65nm technology. Obtained results demonstrate that improvements up to 35.7% in variability factor for leakage power and up to 22.3% in Design Margin for leakage power can be achieved by using the suggested approach.

Citation Download Citation

Sumit Kansal, Marco Lanuzza, and Pasquale Corsonello "Self-repairing SRAM architecture to mitigate the inter-die process variations at 65nm technology", Proc. SPIE 8067, VLSI Circuits and Systems V, 80670X (3 May 2011); https://doi.org/10.1117/12.886873

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