3 May 2011 Analytical modeling of glitch propagation in nanometer ICs
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We present a glitch propagation model that can be used to categorize the propagation likelihood of a given noise waveform trough a logic gate. This analysis is key to predict if a SET induced within a combinational block is capable of causing a SEU. The model predicts the glitch output characteristics given the input noise waveform for each gate in a 65- nm technology library. These noise transfer curves are fitted to known functions to have a simple analytical equation and compute the propagation. Comparison between simulations and model shows a good agreement.
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Xavier Gili, Xavier Gili, Salvador Barceló, Salvador Barceló, Sebastià A. Bota, Sebastià A. Bota, Jaume Segura, Jaume Segura, "Analytical modeling of glitch propagation in nanometer ICs", Proc. SPIE 8067, VLSI Circuits and Systems V, 80670Y (3 May 2011); doi: 10.1117/12.886448; https://doi.org/10.1117/12.886448


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