Through the four years of study in Association of Super-Advanced Electronics Technologies (ASET) on reducing mask
manufacturing Turn Around Time (TAT) and cost, we have been able to establish a technology to improve the efficiency
of the review process by applying a printability verification function that utilizes computational lithography simulations
to analyze defects detected by a high-resolution mask inspection system. With the advent of Source-Mask Optimization
(SMO) and other technologies that extend the life of existing optical lithography, it is becoming extremely difficult to
judge a defect only by the shape of a mask pattern, while avoiding pseudo-defects. Thus, printability verification is
indispensable for filtering out nuisance defects from high-resolution mask inspection results.
When using computational lithography simulations to verify printability with high precision, the image captured by the
inspection system must be prepared with extensive care. However, for practical applications, this preparation process
needs to be simplified. In addition, utilizing Mask Data Rank (MDR) to vary the defect detection sensitivity according to
the patterns is also useful for simultaneously inspecting minute patterns and avoiding pseudo-defects. Combining these
two technologies, we believe practical mask inspection for next generation lithography is achievable.
We have been improving the estimation accuracy of the printability verification function through discussion with several
customers and evaluation of their masks. In this report, we will describe the progress of these practical mask verification
functions developed through customers' evaluations.