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19 May 2011 Collaborative research on emerging technologies and design
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Proceedings Volume 8081, Photomask and Next-Generation Lithography Mask Technology XVIII; 80810N (2011)
Event: Photomask and NGL Mask Technology XVIII, 2011, Yokohama, Japan
Techniques for identifying and mitigating effects of process variation on the electrical performance of integrated circuits are described. These results are from multi-discipline, collaborative university-industry research and emphasize anticipating sources of variation up-stream early in the circuit design phase. The lithography physics research includes design and testing electronic monitors in silicon at 45 nm and fast-CAD tools to identify systematic variations for entire chip layouts. The device research includes the use of a spacer (sidewall transfer) gate fabrication process to suppress random variability components. The Design-for-Manufacturing research includes double pattern decomposition in the presence of bimodal CD behavior, process-aware reticle inspection, tool-aware dose trade-off between leakage and speed, the extension of timing analysis methodology to capture across process-window effects and electrical processwindow characterization.
© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Andrew R. Neureuther, Juliet Rubinstein, Marshal Miller, Kenji Yamazoe, Eric Chin, Cooper Levy, Lynn Wang, Nuo Xu, Costas Spanos, Kun Qian, Kameshwar Poolla, Justin Ghan, Anand Subramanian, Tsu-Jae King Liu, Xin Sun, Kwangok Jeong, Puneet Gupta, Abde Kaqalwalla, Rani Ghaida, and Tuck Boon Chan "Collaborative research on emerging technologies and design", Proc. SPIE 8081, Photomask and Next-Generation Lithography Mask Technology XVIII, 80810N (19 May 2011);

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