23 September 2011 Design issue analysis for InAs nanowire tunnel FETs
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Proceedings Volume 8102, Nanoengineering: Fabrication, Properties, Optics, and Devices VIII; 81020O (2011); doi: 10.1117/12.894249
Event: SPIE NanoScience + Engineering, 2011, San Diego, California, United States
Abstract
InAs nanowire-tunnel eld eect transistors (NW-TFETs) are being considered for future, beyond-Si electronics. They oer the possibility of beating the ideal thermal limit to the inverse subthreshold slope of 60 mV/dec and thus promise reduced power operation. However, whether the tunneling can provide sucient on-current for high-speed operation is an open question. In this work, for a p-i-n device, we investigate the source doping level necessary to achieve a target on-current (1 A) while maintaining a high ION=IOFF ratio (1106) for a range of NW diameters (2 -8 nm). With a xed drain bias voltage and a maximum gate overdrive, we compare the performance in terms of the inverse subthreshold slope (SS) and ION=IOFF ratio as a function of NW- diameter and source doping. As expected, increasing the source doping level increases the current as a result of the reduced screening length and increased electric eld at source which narrows the tunnel barrier. However, since the degeneracy is also increasing, it moves the eective energy window for tunneling away from the barrier where it is the narrowest. This, in turn, tends to decrease the current for a given voltage which, along with the consideration of inverse SS and ION=IOFF ratio leads to an optimum choice of source doping.
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Somaia Sarwat Sylvia, M. Abul Khayer, Khairul Alam, Roger K. Lake, "Design issue analysis for InAs nanowire tunnel FETs", Proc. SPIE 8102, Nanoengineering: Fabrication, Properties, Optics, and Devices VIII, 81020O (23 September 2011); doi: 10.1117/12.894249; https://doi.org/10.1117/12.894249
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KEYWORDS
Doping

Nanowires

Indium arsenide

Field effect transistors

3D modeling

Device simulation

Quantum cascade lasers

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