20 September 2011 See-through-silicon inspection application studies based on traditional silicon imager
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With semiconductor development processes hitting harder and harder on Moore's law to continuously scale down, high density advanced packaging technologies become a promising alternate route to improve transistor density. Chip integration IO/cm2 density jumps quickly by orders from 2D packaging of 102 to wire bonded chip stack of 103, to TSV of 104~105 and to advanced 3D integration of 105 to 106. Starting with wire bonding and now prevailing with TSV, more and more silicon layers are stacked up in 3D dimension to improve system density. A typical stacked wafer sample has two wafers glued together with patterned area sandwiched in between. Outer surfaces can be polished or unpolished bare silicon surface, or patterned surface.
© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Wei Zhou, Darcy Hart, Noah Bock, Rolf Shervey, "See-through-silicon inspection application studies based on traditional silicon imager", Proc. SPIE 8105, Instrumentation, Metrology, and Standards for Nanomanufacturing, Optics, and Semiconductors V, 81050H (20 September 2011); doi: 10.1117/12.892576; https://doi.org/10.1117/12.892576

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