As semiconductor features shrink in size and pitch, the extreme control of CD uniformity, MTT and image placement
is needed for mask fabrication with e-beam lithography. Among the many sources of CD and image placement error,
the error resulting from e-beam mask writer becomes more important than before. CD and positioning error by e-beam
mask writer is mainly related to the imperfection of e-beam deflection accuracy in optic system and the charging and
contamination of column. To avoid these errors, the e-beam mask writer should be designed taking into account for
these effects. However, the writing speed is considered for machine design with the highest priority, because the e-beam
shot count is increased rapidly due to design shrink and aggressive OPC. The increment of shot count can make the
pattern shift problem due to statistical issue resulting from e-beam deflection error and the total shot count in layout.
And it affects the quality of CD and image placement too.
In this report, the statistical approach on CD and image placement error caused by e-beam shot position error is
presented. It is estimated for various writing conditions including the intrinsic e-beam positioning error of VSB writer.
From the simulation study, the required e-beam shot position accuracy to avoid pattern shift problem in 22nm node and
beyond is estimated taking into account for total shot count. And the required local CD uniformity is calculated for
various e-beam writing conditions. The image placement error is also simulated for various conditions including e-beam
writing field position error. Consequently, the requirements for the future e-beam mask writer and the writing
conditions are discussed. And in terms of e-beam shot noise, LER caused by exposure dose and shot position error is
studied for future e-beam mask writing for 22nm node and beyond.