14 October 2011 Anticipation of dimensional issues caused by topography during photo lithography
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Proceedings Volume 8166, Photomask Technology 2011; 81663J (2011); doi: 10.1117/12.896827
Event: SPIE Photomask Technology, 2011, Monterey, California, United States
Abstract
The thickness for a material to be used for photolithography process is typically monitored on test wafers with a completely flat surface. Therefore material's specification is limited to thickness uniformity, reflectance, refractive indexes and chemical properties. NVM embedded IC's integrating a variety of devices within the same chip may lead to challenging topography at gate level. Tight control of transistors CD, coherent with model based OPC treatments precision, is hard to achieve in circuitry regions with small surface before resist coating. The proposed model is based on reflectance increase in areas where observed CD is small with respect to the target. The observed root cause of CD loss is linked with materials' behavior in the proximity of edges of silicon structures and with the overall thickness reduction when the blocks become small. A set of test patterns is defined and substrates are prepared with planarizing and conformal BARC's to quantify the influence of topography on the CD. The geometries provide a good sampling in terms surface. After lithography, the dimensional effects are quantified by top view SEM. A model describing materials thinning can be computed from CD behavior data in the case of inorganic BARC. The study shows the limitations of both types of BARC's and suggests that Optical Proximity Correction could be used to compensate the effects of topography. Some recommendations are made in order to fulfill 65nm and smaller technology nodes' requirements. Several components of the study can be combined to master topography effects in complex process flows.
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Lionel Ravel, Christophe Brault, Chloé Hegaret, Antonio Di Giacomo, Romain Lallement, Jérôme Azémar, Marie Hellion, "Anticipation of dimensional issues caused by topography during photo lithography", Proc. SPIE 8166, Photomask Technology 2011, 81663J (14 October 2011); doi: 10.1117/12.896827; https://doi.org/10.1117/12.896827
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KEYWORDS
Transistors

Critical dimension metrology

Photomasks

Lithography

Optical proximity correction

Etching

Reflectivity

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