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13 October 2011 Towards the prediction of pattern collapse hotspots for full-chip layouts
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Abstract
Critical aspect ratio induced pattern collapse has been a concern for lithography process engineers since before the 180 nm node. This has driven a steady reduction in photoresist thickness, as well as accelerated the introduction of hard mask materials and processes. There have been multiple studies and proposed models for the fundamental forces which lead to pattern collapse, with consensus being that differential capillary forces across opposing sides of a developed photoresist line during the water rinse/dry step are responsible for line bending. This line bending can lead to pattern deformation or complete substrate adhesion failure. Several process improvements, such as surfactant-laced final rinse, have been proposed to alter surface energies and increase the critical aspect ratio for collapse. The mechanical models which have been proposed to explain this phenomenon have all been effectively two-dimensional, characterizing the aspect ratio (Z/X) for an idealized pattern assumed to be semi-infinite in the Y dimension. While these models are very helpful for guiding materials/process understanding and improvement, they are not as helpful in predicting real random logic "hotspots": pattern locations most likely to fail through the manufacturing process window. This work proposes a framework for full-chip prediction of pattern collapse failure by use of a semi-empirical model and an efficient geometric checking engine. Idealized test patterns are studied initially, in order to reproduce behaviors commonly reported in the literature for semiinfinite Y patterns, and then more complex layout configurations are introduced. It is shown that full-chip pattern collapse can be efficiently and accurately predicted. Such a capability can prove valuable in setting design rules, and in refining RET solutions.
© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
John L. Sturtevant, Aasutosh Dave, and Uwe Hollerbach "Towards the prediction of pattern collapse hotspots for full-chip layouts", Proc. SPIE 8166, Photomask Technology 2011, 81663Y (13 October 2011); https://doi.org/10.1117/12.898494
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