Infrared focal plane detector has a multilayer configuration which consists of substrate, chip, readout IC, Indium
interconnects, epoxy and electrical lead board, it is packaged layer by layer precisely. Because of the difference in
thermal expansion between the layers, with repeated thermal cycling plenty of thermal stress produced by assembling
errors will lead result in failure of the interconnects or lead to damage to the detector pixels. In this paper, based on a
detector-Dewar assembly, we analyze the thermal stress on the detector by different packaging accuracy level. With the
allowable thermal stress, we optimize the processes of the packaging experiment and redesign the fixtures used in the
packaging processes to improve assembly accuracy, on this condition, the detector-Dewar assembly assembled satisfies
our design requirement, and the thermal stress caused by the cooler is below the range permitted.