8 September 2011 Design of readout integrated circuit structure for single and dual band infrared detector with variable integration time
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Abstract
This paper proposes two kinds of readout integrated circuits for column and row interlaced dual-band infrared detectors. The experiments were simulated using TSMC 0.35μm Mixed Signal 2P4M CMOS process and operated at 3MHz clock rate. The pixel dimensions for two kinds of readout integrated circuits were also 30×30μm. The mid-wave and long-wave sense current was set from 1nA to 2nA and 6nA to 8nA, respectively. We designed a 40x16 array for the columns interlace readout circuit. The output voltage swing was 2.8V. The frame rate was 4.68kFPS. The total power consumption was less than 17.6mW. We also designed a 20x32 array for the row interlace readout circuit. The output voltage swing was 2.8V. The frame rate was 2.67kFPS. The total power consumption was less than 11.4mW. The power consumption increased when the column interlace frame rate reached the row interlace frame rate. The row interlace can decrease the layout area by sharing the column stage circuit, but the frame rate will drop to half of the single band frame rate.
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Tai-Ping Sun, Tai-Ping Sun, Yi-Chuan Lu, Yi-Chuan Lu, Hsiu-Li Shieh, Hsiu-Li Shieh, Shiuan-Shuo Shiu, Shiuan-Shuo Shiu, Yi-Ting Liu, Yi-Ting Liu, Shiang-Feng Tang, Shiang-Feng Tang, Wen-Jen Lin, Wen-Jen Lin, } "Design of readout integrated circuit structure for single and dual band infrared detector with variable integration time", Proc. SPIE 8193, International Symposium on Photoelectronic Detection and Imaging 2011: Advances in Infrared Imaging and Applications, 81933V (8 September 2011); doi: 10.1117/12.900963; https://doi.org/10.1117/12.900963
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