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18 August 2011 Image lag optimization of four-transistor pixel for high speed CMOS image
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In this paper the image lag effect in large size 4T pixel for high speed image sensor is simulated and optimized. The image lag is mainly caused by the potential barrier and pocket near the transfer gate edge in large size 4T pixel. The simulation is based on 0.13μm CMOS process. The dependence of the potential barrier and the potential pocket on design and process parameters is studied. We optimize the parameters, such as offset length between P+ layer and N layer, N layer doping energy in pinned photodiode (PPD) and TGVT layer doping dose. The simulation results show that minimum image lag can be obtained at an offset length between P+ and N of 0.3μm, an N layer doping energy of 200KeV and N layer doping dose of 3.5x1012cm-2. The optimizing design effectively improves the charge transfer characteristics of large size 4T pixel and the performance of high speed CMOS image sensor.
© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Yangfan Zhou, Zhongxiang Cao, Quanliang Li, Qi Qin, and Nanjian Wu "Image lag optimization of four-transistor pixel for high speed CMOS image", Proc. SPIE 8194, International Symposium on Photoelectronic Detection and Imaging 2011: Advances in Imaging Detectors and Applications, 819435 (18 August 2011);

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