27 February 2012 VLED for Si wafer-level packaging
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In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.
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Chen-Fu Chu, Chen-Fu Chu, Chiming Chen, Chiming Chen, Jui-Kang Yen, Jui-Kang Yen, Yung-Wei Chen, Yung-Wei Chen, Chingfu Tsou, Chingfu Tsou, Chunming Chang, Chunming Chang, Trung Doan, Trung Doan, Chuong Anh Tran, Chuong Anh Tran, "VLED for Si wafer-level packaging", Proc. SPIE 8262, Gallium Nitride Materials and Devices VII, 82621J (27 February 2012); doi: 10.1117/12.910062; https://doi.org/10.1117/12.910062

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