Hardware accelerator design for change detection in smart camera

Sanjay Singh; Srinivasa Murali Dunga; Ravi Saini; A. S. Mandal; Chandra Shekhar; Santanu Chaudhury; Anil Vohra

doi:10.1117/12.913591

1 October 2011 Hardware accelerator design for change detection in smart camera

Sanjay Singh; Srinivasa Murali Dunga; Ravi Saini; A. S. Mandal; Chandra Shekhar; Santanu Chaudhury; Anil Vohra

Author Affiliations +

Proceedings Volume 8285, International Conference on Graphic and Image Processing (ICGIP 2011); 82852T (2011) https://doi.org/10.1117/12.913591
Event: 2011 International Conference on Graphic and Image Processing, 2011, Cairo, Egypt

Abstract

Smart Cameras are important components in Human Computer Interaction. In any remote surveillance scenario, smart cameras have to take intelligent decisions to select frames of significant changes to minimize communication and processing overhead. Among many of the algorithms for change detection, one based on clustering based scheme was proposed for smart camera systems. However, such an algorithm could achieve low frame rate far from real-time requirements on a general purpose processors (like PowerPC) available on FPGAs. This paper proposes the hardware accelerator capable of detecting real time changes in a scene, which uses clustering based change detection scheme. The system is designed and simulated using VHDL and implemented on Xilinx XUP Virtex-IIPro FPGA board. Resulted frame rate is 30 frames per second for QVGA resolution in gray scale.

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Sanjay Singh, Sanjay Singh, Srinivasa Murali Dunga, Srinivasa Murali Dunga, Ravi Saini, Ravi Saini, A. S. Mandal, A. S. Mandal, Chandra Shekhar, Chandra Shekhar, Santanu Chaudhury, Santanu Chaudhury, Anil Vohra, Anil Vohra, } "Hardware accelerator design for change detection in smart camera", Proc. SPIE 8285, International Conference on Graphic and Image Processing (ICGIP 2011), 82852T (1 October 2011); doi: 10.1117/12.913591; https://doi.org/10.1117/12.913591

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