1 October 2011 A VLSI architecture for real-time signal FFT based on pipelined processing element
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Proceedings Volume 8285, International Conference on Graphic and Image Processing (ICGIP 2011); 82855K (2011) https://doi.org/10.1117/12.913420
Event: 2011 International Conference on Graphic and Image Processing, 2011, Cairo, Egypt
Abstract
In this paper, a VLSI architecture for real-time signal FFT based on pipelined processing element (PE) is proposed. The proposed architecture suits to FFT/ IFFT and supports input/ output simultaneously. In the system a 2MN point FFT can be computed by 2M point row-wise FFT followed by 2N point column-wise 2-D FFT. By this way long length FFT is divided continuously until it could be conquered by some short length processing elements (PE). The proposed pipelined PE architectures are based on short length FFT algorithms used in WFTA, so multiplier number in PEs is minimal. A 1024-point complex FFT is implemented in XC2VP30-7 FPGA board based on the VLSI architecture. Result shows that latency between input and output is about 3300 clock cycles, and the computation time for real-time signal FFT is minimal compare to recent research. The proposed architecture also has flexible configuration for different point FFT.
© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Xu Wang, Xu Wang, Yan Zhang, Yan Zhang, Jiannan Wang, Jiannan Wang, } "A VLSI architecture for real-time signal FFT based on pipelined processing element", Proc. SPIE 8285, International Conference on Graphic and Image Processing (ICGIP 2011), 82855K (1 October 2011); doi: 10.1117/12.913420; https://doi.org/10.1117/12.913420
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