This PDF file contains the front matter associated with SPIE Proceedings Volume 8323, including the Title Page, Copyright information, Table of Contents, and the Conference Committee listing.

The crossover of high-speed digital electronics, MEMS, and cost reduction presents an exciting opportunity to extend optical lithography with multiple e-beam direct write systems. Massive parallelism overcomes the throughput limitation of e-beam direct write systems. Many innovative concepts on multiple e-beam imaging have been conceived and are being developed for various applications, such as maskwriting, prototyping, writing critical layers in high volume manufacturing (HVM), and writing all layers in HVM. MEB DW systems are capable to do all of the above. For maskwriting, the writing time can be saved by between a factor of 5 and 10 but it takes similar efforts to develop the maskwriting technology as direct wafer writing. There is insufficient demand for maskwriting and prototyping tools to warrant the development efforts. Writing critical layers in HVM makes economic sense for wafer production and makes economic sense to develop the imaging tool. However, using MEB DW for critical and non-critical layers, especially for 450-mm wafers, presents a unique opportunity to save lithography cost for the 450-mm wafer technology. This is the most desirable application for MEB DW. Once this application is established, all other applications easily follow.

The use of block copolymer self-assembly for device fabrication in the semiconductor industry has been envisioned for over a decade. Early works by the groups of Hawker, Russell, and Nealey [1-2] have shown a high degree of dimensional control of the self-assembled features over large areas with high degree of ordering. The exquisite dimensional control at nanometer-scale feature sizes is one of the most attractive properties of block copolymer self-assembly. At the same time, device and circuit fabrication for the semiconductor industry requires accurate placement of desired features at irregular positions on the chip. The need to coax the self-assembled features into circuit layout friendly location is a roadblock for introducing self-assembly into semiconductor manufacturing. Directed self-assembly (DSA) and the use of topography to direct the self-assembly (graphoepitaxy) have shown great promise in solving the placement problem [3-4]. In this paper, we review recent progress in using block copolymer directed self-assembly for patterning sub-20 nm contact holes for practical circuits.

Design considerations for UV-NIL resists were investigated focusing on the major issues of ink-jetting performance, pattern formability, release property, and dry etching resistance. Regarding ink-jetting performance, small droplet inkjetting of 0.7pl was successfully demonstrated by adjusting the resist fluid property to the ink-jet coater and controlling the resist volatilization. Regarding pattern formability, a resist pattern was imprinted from a mold pattern of 28nm in width and 60nm in depth without pattern dimension change. It was thought that modulus control of the resist was more important than resist shrinkage in achieving excellent pattern formability. As for release property, resist with fluorine monomer and with non-reactive fluorine anti-sticking agent were compared. The results indicated that resist design has the capability to both reduce separation force and maintain a clear mold surface. The mold release agent decomposed with increasing number of imprint shots, but the low release force resist with non-reactive anti-sticking agent was able to control degradation of the mold release agent and thus improve release property endurance. Regarding etching resistance, it was found that increasing the ring parameter of resist is essential for high etching resistance, and resulted in improved etched pattern features of the substrate.

Nanoimprint lithography is conventionally used to transfer a pattern from a mold to a deformable and curable resist layer. Here we report a nanoimprinting technique to selectively transfer components of a pre-assembled nanostructure to a new substrate, while retaining the advantages of nanoimprint lithography such as low cost and high throughput. We use this technique to study metal particle roughness in Au "nanofinger" substrates, along with the effects of annealing to reduce roughness, and the impact of annealing on the Surface Enhanced Raman Scattering (SERS) signal. The nanofinger substrates consist of Au-coated polymer pillars arranged to collapse into a designed assembly. Upon exposure to a volatile liquid and subsequent drying, microcapillary forces pull the pillars and their metal caps together into the designed structure. Successful transfer was achieved using the concept of template stripping via cold welding using a normal nanoimprinting process with no resist layer but under appropriate pressure to ensure even and complete transfer of all the nanostructures. Particle roughness was not found to be a significant factor in SERS from naonfinger substrates as annealing did not increase the observed Raman intensity.

Directed self-assembly (DSA) has the potential to extend scaling for both line/space and hole patterns. DSA has shown the capability for pitch reduction (multiplication), hole shrinks, CD self-healing as well as a pathway towards line edge roughness (LER) and pattern collapse improvement [1-4]. The current challenges for industry adoption are materials maturity, practical process integration, hardware capability, defect reduction and design integration. Tokyo Electron (TEL) has created close collaborations with customers, consortia and material suppliers to address these challenges with the long term goal of robust manufacturability. This paper provides a wide range of DSA demonstrations to accommodate different device applications. In collaboration with IMEC, directed line/space patterns at 12.5 and 14 nm HP are demonstrated with PS-b-PMMA (poly(styrene-b-methylmethacrylate)) using both chemo and grapho-epitaxy process flows. Pre-pattern exposure latitudes of >25% (max) have been demonstrated with 4X directed self-assembly on 300 mm wafers for both the lift off and etch guide chemo-epitaxy process flows. Within TEL's Technology Development Center (TDC), directed selfassembly processes have been applied to holes for both CD shrink and variation reduction. Using a PS-b-PMMA hole shrink process, negative tone developed pre-pattern holes are reduced to below 30 nm with critical dimension uniformity (CDU) of 0.9 nm (3s) and contact edge roughness (CER) of 0.8 nm. To generate higher resolution beyond a PS-b-PMMA system, a high chi material is used to demonstrate 9 nm HP line/ space post-etch patterns. In this paper, TEL presents process solutions for both line/space and hole DSA process integrations.

Directed Self-Assembly (DSA) of block copolymers is considered to be a potential lithographic solution to achieve higher feature densities than can be obtained by current lithographic techniques. However, it is still not well-established how amenable DSA of block copolymers is to an industrial fabrication environment in terms of defectivity and processing conditions. Beyond production-related challenges, precise manipulation of the geometrical and chemical properties over the substrate is essential to achieve high pattern fidelity upon the self-assembly process. Using our chemo-epitaxy DSA approach offers control over the surface properties of the slightly preferential brush material as well as those of the guiding structures. This allows for a detailed assessment of the critical material parameters for defect reduction. The precise control of environment afforded by industrial equipment allows for the selective analysis of material and process related boundary conditions and assessment of their effect on defect generation. In this study, the previously reported implementation of our feature multiplication process was used to investigate the origin of defects in terms of the geometry of the initial pre-patterns. Additionally, programmed defects were used to investigate the ability of the BCP to heal defects in the resist patterns and will aid to assess the capture capability of the inspection tool. Finally, the set-up of the infrastructure that will allow the study the generation of defects due to the interaction of the BCP with the boundary conditions has been accomplished at imec.

The fluorine-containing block copolymers of poly(styrene-block-2,2,2-trifluoroethyl methacrylate) (PS-b-PTFEMA) and poly(4-hydroxystyrene-block-2,2,2-trifluoroethyl methacrylate) (PHOST-b-PTFEMA), which all are capable of both top-down and bottom-up lithography were developed. The reported block copolymers were synthesized by either anionic polymerization or atom transfer radical polymerization (ATRP). Characterization of bulk and thin films were carried out using differential scanning calorimetry (DSC), transmission electron microscopy (TEM) and small angle X-ray scattering (SAXS). Thin films of the resulting block copolymers were subjected to conventional lithographic processing using e-beam and deep-UV radiation to create integrated patterns such as dots in lines.

A roadmap extending far beyond the current 22nm CMOS node has been presented several times. [1] This roadmap includes the use of a highly regular layout style which can be decomposed into "lines and cuts."[2] The "lines" can be done with existing optical immersion lithography and pitch division with self-aligned spacers.[3] The "cuts" can be done with either multiple exposures using immersion lithography, or a hybrid solution using either EUV or direct-write ebeam.[ 4] The choice for "cuts" will be driven by the availability of cost-effective, manufacturing-ready equipment and infrastructure. Optical lithography improvements have enabled scaling far beyond what was expected; for example, soft x-rays (aka EUV) were in the semiconductor roadmap as early as 1994 since optical resolution was not expected for sub-100nm features. However, steady improvements and innovations such as Excimer laser sources and immersion photolithography have allowed some manufacturers to build 22nm CMOS SOCs with single-exposure optical lithography. With the transition from random complex 2D shapes to regular 1D-patterns at 28nm, the "lines and cuts" approach can extend CMOS logic to at least the 7nm node. The spacer double patterning for lines and optical cuts patterning is expected to be used down to the 14nm node. In this study, we extend the scaling to 18nm half-pitch which is approximately the 10-11nm node using spacer pitch division and complementary e-beam lithography. For practical reasons, E-Beam lithography is used as well to expose the "mandrel" patterns that support the spacers. However, in a production mode, it might be cost effective to replace this step by a standard 193nm exposure and applying the spacer technique twice to divide the pitch by 3 or 4. The Metal-1 "cut" pattern is designed for a reasonably complex logic function with ~100k gates of combinatorial logic and flip-flops. Since the final conductor is defined by a Damascene process, the "cut" patterns become islands of resist blocking hard-mask trenches. The shapes are often small and positioned on a dense grid making this layer to be the most critical one. This is why direct-write e-beam patterning, possibly using massively parallel beams, is well suited for this task. In this study, we show that a conventional shaped beam system can already pattern the 11nm node Metal-1 layer with reasonable overlay margin. The combination of design style, optical lithography plus pitch-division, and e-beam lithography appears to provide a scaling path far into the future.

First results obtained with IMS Nanofabrication's 50keV proof-of-concept electron multi-beam mask exposure tool (eMET POC) are presented. The eMET POC was designed from scratch to meet the requirements of the 11nm half-pitch node and features already the same column as future high volume manufacturing (HVM) tools. All exposures shown in this paper were the result of 262,144 beams of 20nm beam size working in parallel demonstrating the capability of IMS' multi-beam technology. An Alpha Tool is scheduled for 2014, followed by a Beta Tool in 2015 and 1^st generation HVM Tools in 2016.

Maskless electron beam lithography can potentially extend semiconductor manufacturing to the 16 nm technology node and beyond. KLA-Tencor is developing Reflective Electron Beam Lithography (REBL) targeting high-volume 16 nm half pitch (HP) production. This paper reviews progress in the development of the REBL system towards its goal of 100 wph throughput for High Volume Manufacturing (HVM) at the 2X and 1X nm nodes. We will demonstrate the ability to print TSMC test patterns with the integrated system in photoresist on silicon wafers at 45 nm resolution. Additionally, we present simulation and experimental results that demonstrate that the system meets performance targets for a typical foundry product mix. Previously, KLA-Tencor reported on the development of a REBL tool for maskless lithography at and below the 16 nm HP technology node1. Since that time, the REBL team and its partners (TSMC, IMEC) have made good progress towards developing the REBL system and Digital Pattern Generator (DPG) for direct write lithography. Traditionally, e-beam direct write lithography has been too slow for most lithography applications. E-beam direct write lithography has been used for mask writing rather than wafer processing since the maximum blur requirements limit column beam current - which drives e-beam throughput. To print small features and a fine pitch with an e-beam tool requires a sacrifice in processing time unless one significantly increases the total number of beams on a single writing tool. Because of the continued uncertainty with regards to the optical lithography roadmap beyond the 16 nm HP technology node, the semiconductor equipment industry is in the process of designing and testing e-beam lithography tools with the potential for HVM.

We report on Finite Element Modeling (FEM) of the influence of heat load due to the lithographic exposure on the inplane distortion (IPD) of 450 mm Si-wafers and hence on the effect of the heat load on the achievable image placement accuracy. Based on a scenario of electron beam writing at an exposure power of 20 mW, the thermo-mechanical behavior of the chuck and the attached Si wafer is modeled and used to derive corresponding IPD values. To account for the pin structured chuck surface, an effective layer model is derived. Different materials for the wafer chuck are compared with respect to their influence on wafer IPD and thermal characteristics of the exposure process. Guidelines for the selection of the chuck material und suggestions for its cooling and corrective strategies on e-beam steering during exposure are derived.

We use Self-Consistent Field Theory (SCFT) to study the directed self-assembly of laterally confined diblock copolymers. In this study, we focus on systems where the self-assembled lamellae are oriented parallel to the selective sidewalls of the channel. While well-ordered, perfect lamellae are observed both experimentally and numerically, undesirable defective structures also emerge. We therefore investigate the energetics of two isolated defects, dislocations and disclinations, for various chain lengths and channel dimensions and establish conditions that favor the formation of defects. We also determine the energy barrier and the transition path between the defective and perfect state using the string method.

The main concern for the commercialization of directed self-assembly (DSA) for semiconductor manufacturing continues to be the uncertainty in capability and control of defect density. Our research investigates the defect densities of various DSA process applications in the context of a 300mm wafer fab cleanroom environment; this paper expands substantially on the previously published DSA defectivity study by reporting a defect density process window relative to chemical epitaxial pre-pattern registration lines; as well as investigated DSA based contact hole shrinking and report critical dimension statistics for the phase separated polymers before and after etch, along with positional accuracy measurements and missing via defect density.

In this paper we investigate the possibility to reach 300mm CMOS requirements by integrating graphoepitaxy of PS-b-PMMA self-assembly. Different schemes to integrate DSA process by using 193nm dry lithography or e-Beam lithography will be presented. Moreover, several challenges like solvent compatibility, bake kinetics and defectivity will be addressed. Concerning defectivity, we will propose a methodology in order to evaluate and optimize the long range order induced by graphoepitaxy of the block copolymer DSA. This approach affords the monitoring of the overall block copolymer self-assembly process and enables us to easily optimize the parameters required for a long-range order structuration, leading to a near zero-defects block copolymers self-assembled arrays. Transfer capabilities of the PS masks in the bulk silicon substrate by using plasma-etching will be also detailed, both with the film on bare silicon or organized with graphoepitaxy approaches. These results show the high potential of DSA to be integrated directly into the conventional CMOS lithography process in order to achieve high resolution and pattern density multiplication, at a low cost.

Extensive pattern customization will be necessary to realize viable circuit patterns from line-space arrays generated by block copolymer directed self assembly (DSA). In pattern customization with regard to chemical epitaxy of lamellar block copolymers, quantitative and precise knowledge of DSA-feature registration to the chemical prepattern is critical. Here we measure DSA pattern placement error for spatial frequency tripling and quadrupling indexed to specific lines in the chemical prepattern. A range of prepattern line widths where minimal DSA placement error can be expected is identified, and a positive correlation between DSA placement accuracy and prepattern uniformity is shown. Considering the experimental non-idealities present in the chemical prepatterns used in this work that arise from using electron-beam lithography, we anticipate that 3σ DSA placement errors will be at a minimal level if highly uniform chemical prepatterns produced by optical lithography are used.

Bit patterned media (BPM) is a promising candidate for next-generation magnetic recording media beyond 2.5 Tb/in2. To realize such high-density patterned media, directed self-assembling (DSA) technology is a possible solution to form fine dots. In order to read and write magnetic signals on a magnetic dot of magnetic media, the position of magnetic dots must be controlled. We examined ordering of directed self-assembly of diblock copolymer dots with a variety of prepatterned guides in some conditions and evaluated the ordering of the dots by using Delaunay triangulation and Voronoi diagram. Applying the optimized conditions, we obtained highly controlled dot pattern suitable for magnetic recording media.

Directed self-assembly is emerging as a promising technology to define sub-20nm features. However, a straightforward path to scale block copolymer lithography to single-digit fabrication remains challenging given the diverse material properties found in the wide spectrum of self-assembling materials. A vast amount of block copolymer research for industrial applications has been dedicated to polystyrene-b-methyl methacrylate (PS-b-PMMA), a model system that displays multiple properties making it ideal for lithography, but that is limited by a weak interaction parameter that prevents it from scaling to single-digit lithography. Other block copolymer materials have shown scalability to much smaller dimensions, but at the expense of other material properties that could delay their insertion into industrial lithographic processes. We report on a line doubling process applied to block copolymer patterns to double the frequency of PS-b-PMMA line/space features, demonstrating the potential of this technique to reach single-digit lithography. We demonstrate a line-doubling process that starts with directed self-assembly of PS-b-PMMA to define line/space features. This pattern is transferred into an underlying sacrificial hard-mask layer followed by a growth of self-aligned spacers which subsequently serve as hard-masks for transferring the 2x frequency doubled pattern to the underlying substrate. We applied this process to two different block copolymer materials to demonstrate line-space patterns with a half pitch of 11nm and 7nm underscoring the potential to reach single-digit critical dimensions. A subsequent patterning step with perpendicular lines can be used to cut the fine line patterns into a 2-D array of islands suitable for bit patterned media. Several integration challenges such as line width control and line roughness are addressed.

The use of bit pattern media beyond densities of 1Tb/in² requires the ability to pattern dimensions to sub 10nm. This paper describes the techniques used to reach these dimensions with imprint lithography and avoid such challenges as pattern collapse, by developing improved resist materials with higher strength, and utilizing a reverse tone J-FIL/R process.

Block copolymer directed self-assembly (DSA) is a promising extension of optical lithography for device fabrication akin to double-patterning. The irregular distribution of contact holes in circuit layouts is one of the biggest challenges for DSA patterning because the self-assembly tends to form regular patterns naturally. Although the small guiding templates are shown to guide the self-assembly off the natural geometry by strong boundary confinement [1, 2] (Fig. 1), it is insufficient to simply surround contact holes with guiding templates without optimizing the placement and geometry of the guiding templates.

A photomask design flow for generating guiding patterns used in graphoepitaxial DSA processes is proposed and tested. In this flow, a new fast DSA model is employed for DSA structure verification. The execution speed and accuracy of the fast model were benchmarked with our previously reported Monte Carlo method. We demonstrated the process window verification using the OPC/DSA flow with the fast DSA model and compared this with experimental results in the guiding patterns simulated by e-beam lithography.

We report on a contact hole shrink process using directed self-assembly. A diblock copolymer, poly (styrene-blockmethyl methacrylate) (PS-b-PMMA), is used to shrink contact holes. Contact hole guide patterns for graphoepitaxy are formed by ArF photoresists. Cylindrical domains of PMMA is removed using organic solvents after DUV (λ <200 nm) irradiation. In this work, it is found that a solvent system is the best developer from the evaluated single solvent systems and mixed solvent systems. The wet development of PS-b-PMMA strongly depends on total exposure dose of DUV irradiation. With lower exposure dose, the cylindrical domains of PMMA are not clearly removed. With optimum exposure dose, PMMA is developed clearly. The contact hole guide patterns of 75 nm in diameter are successfully shrunk to 20 nm in diameter using the wet development process.

Directed self assembly (DSA) of block copolymers (BCP) could enable high resolution secondary patterning via pitch multiplication from lower resolution primary lithographic patterns. For example, DSA could enable dense feature production at pitches less than 20 nm from patterns generated using 193 nm exposure tools. According to theory, microphase separation of block copolymers can only occur when the critical condition that χ^N>10.5 is met, where χ is the Flory Huggins interaction parameter and N is the total degree of polymerization for the block copolymer. In order to generate smaller DSA pattern pitches, the degree of polymerization of the block copolymer is reduced since this reduces the characteristic length scale for the polymer (e.g. radius of gyration). Thus, as N is reduced, the effect of this reduction on χ^N must be balanced by increasing χ to maintain a given level of phase separation. Currently, most DSA work has focused on the use of poly(styrene)-b-poly(methyl methacrylate) (PS-b-PMMA) copolymers whose low χ value (i.e. ~0.04) limits the practical DSA pitch using such materials to approximately 20nm. The general goal of this work has been to explore new higher χ block copolymer systems, develop DSA patterning schemes based on such materials, and test their ultimate pitch resolution. This paper discusses the synthesis and characterization of poly(styrene)-b-poly(hydroxystyrene) (PS-b-PHOST) copolymers made via nitroxide mediated radical polymerization. The formation of lamellar fingerprint structures in PS-b-PHOST using solvent annealing is demonstrated. Using this fingerprint data, initial estimates of χ for PS-b-PHOST are made which show that it appears to be at least one order of magnitude larger than the χ for PS-b-PMMA . Finally, graphoepitaxy of self-assembled lamellar structures in PS-b-PHOST is demonstrated using SU-8 guiding patterns on cross-linked neutral underlayers.

REBL (Reflective Electron Beam Lithography) is a novel concept for high speed maskless projection electron beam lithography. Originally targeting 45 nm HP (half pitch) under a DARPA funded contract, we are now working on optimizing the optics and architecture for the commercial silicon integrated circuit fabrication market at the equivalent of 16 nm HP. The shift to smaller features requires innovation in most major subsystems of the tool, including optics, stage, and metrology. We also require better simulation and understanding of the exposure process. In order to meet blur requirements for 16 nm lithography, we are both shrinking the pixel size and reducing the beam current. Throughput will be maintained by increasing the number of columns as well as other design optimizations. In consequence, the maximum stage speed required to meet wafer throughput targets at 16 nm will be much less than originally planned for at 45 nm. As a result, we are changing the stage architecture from a rotary design to a linear design that can still meet the throughput requirements but with more conventional technology that entails less technical risk. The linear concept also allows for simplifications in the datapath, primarily from being able to reuse pattern data across dies and columns. Finally, we are now able to demonstrate working dynamic pattern generator (DPG) chips, CMOS chips with microfabricated lenslets on top to prevent crosstalk between pixels.

This paper presents our designed and prototyped structure of electron emitter array integrated with an active-matrix driving LSI for high-speed massively parallel direct-write electron-beam (e-beam) system. In addition, the validation results of its performance as an electron source for massively parallel operation are described. Electron source used in this system is nanocrystalline Si (nc-Si) ballistic surface electron emitter where 1:1 projection of e-beam has been demonstrated to resolve patterns of 30 nm in width in our previous work. Electron emitting part of the device consists of arrayed dots of nc-Si emitter fabricated on SOI or Si substrate, and TSV (Through Silicon Via) plugs connected to the dots from back side of the substrate. Forming an aligned joint of the TSV plugs with driving pads on the active-matrix LSI constitutes the device. Electron emission is driven by the LSI operation, boosted up to appropriate level by the builtin voltage level shifter, in accordance with a bitmap image preliminarily stored in an embedded memory. Electron emission from a test structure of arrayed dot patterns of nc-Si emitter worked in practice, showing the possibility to switch on and off the beamlets by changing CMOS-compatible voltage.

We successfully demonstrate complementary patterning with self-aligned double patterning (SADP) and currently used e-beam direct writer (EBDW). The complementary patterning is achieved with not only positive type pattern for gate layer but also negative type one for 1st metal (M1) layer at 11nm node. The e-beam exposure is performed by Advantest. SADP process before e-beam exposure and etching after e-beam exposure are performed by Tokyo Electron. This paper also reports EBDW applicability to complementary patterning for 8nm node and beyond in the light of overlay and resolution, and improving plans including shot number reduction.

We had previously established CP (character projection) based EBDW technology for 65nm and 45nm device production. And recently we have confirmed the resolution of 14nm L&S patterns which meets 14nm and beyond node logic requirement with CP exposure. From these production achievement and resolution potential, with multi-beam EBDW and CP function, MCC [1] could be one of the most promising technologies for future high volume manufacturing if exposure throughput was drastically enhanced. We have set target throughput as 100 WPH to meet HVM (high volume manufacturing) requirement. Our designed parameters to attain 100 WPH for 14nm result in 150 beams, 10cluster, 100 Giga shots/wafer, 250A/cm^2 and 75uC/cm^2. In addition to multi-beam, drastic exposure shot reduction is indispensable to attain 100 WPH for 14nm node. We have aggressively targeted 100 Giga shot count which is equivalent to covering 300mm wafer with 0.8um x 0.8um square fairly large tile. All device circuit blocks should be structured with only CP defined parts and we should trace back to upstream design flow to RTL. We call this methodology "CP element based design". In near future, Litho-Friendly restricted design would be commonly used [3] [4]. Our CP defined tile based regular layout would be highly compatible with these ultra-regular design approaches. The primal design factors are Logic cell, Memory macro and random interconnect. We have established concepts to accomplish high volume production with CP-based EBDW at 14nm technology node.

We studied the erosion and feature stability of fused silica patterns under different template cleaning conditions. The conventional SPM cleaning is compared with an advanced non-acid process. Spectroscopic ellipsometry optical critical dimension (SE-OCD) measurements were used to characterize the changes in pattern profile with good sensitivity. This study confirmed the erosion of the silica patterns in the traditional acid-based SPM cleaning mixture (H2SO4+H2O2) at a rate of ~0.1nm per cleaning cycle. The advanced non-acid clean process however only showed CD shift of ~0.01nm per clean. Contamination removal & pattern integrity of sensitive 20nm features under MegaSonic assisted cleaning is also demonstrated.

We combine block copolymer directed self-assembly with nanoimprint lithography to generate templates with rectangular patterns through an original double imprint process. We use a rotary e-beam tool to separately expose circumferential and radial line/space chemical contrast patterns with periodicities commensurate to the natural period of two lamellae-forming poly(styrene-b-methyl methacrylate) (PS-b-PMMA) block copolymers. Line patterns are formed by directed self-assembly of PS-b-PMMA on chemical patterns on two separate submaster templates, one with circumferential lines to define concentric tracks, and a second template on which the block copolymer is used to form radial lines at constant angular pitch. The patterns are subsequently transferred to their underlying Si substrates to form submaster templates. Using two sequential nanoimprinting steps, we combine the radial and circumferential submaster line patterns into a final quartz master template with rectangular bits on circular tracks.

Soft imprint templates trend to deformation when imprint forces are added. This deformation occurs both in the macro aspect (unevenness of the imprint resist layer through the whole imprint area) and in the micro aspect (deformation of single structure). These deformations will be transferred directly to the imprint resist after its curing and thus influence the imprint results. An understanding of these deformation behaviors depending on the template geometry and the imprint process parameters is necessary for the process development. In this work the deformation behaviors of the polymer soft imprint template was analyzed using finite element method (FEM) and experimentally investigated.

Sealed nanofluidic channels with cross sections of sub-100 nm * 100 nm were created in a polymer bilayer using the focused soft X-rays of a scanning transmission X-ray microscope and the direct write method. The width of the nanochannels can be controlled by the area patterned in X and Y, while the height can be controlled by tuning the layer thicknesses. Formation of the desired structures has been confirmed by near edge X-ray absorption fine structure spectromicroscopy and scanning electron microscopy. The maximum length of the nanochannels fabricated by this method was found to be limited by the efficiency of excavation of patterned material out of the channel, as well as the stability of the polymer over-layer which seals it. Schemes toward interfacing these nanochannels with conventional microfluidics are discussed.

To keep on with scaling down of nanoelectronic components novel lithographic approaches are required. The direct, positive-tone lithography of calixarene molecular resists by scanning probe techniques represents a promising alternative for ease-of-use sub-10 nm mask-less lithography. Herein, we demonstrate a closed loop tip-based nanolithography using the same nanoprobe for: (i) AFM pre-imaging for pattern overlay alignment; (ii) direct writing of features into calixarene molecular resist applying a highly confined, development-less removal process; and (iii) AFM post-imaging as final in-situ inspection. In addition, we demonstrate parallel writing capabilities by employing multi nano-tip probes. By using these methods we can drastically enhance the attractiveness of calixarene molecular resist as development-less, high resolution resist material for Scanning Probe Lithography (SPL).

Roll-to-Roll (R2R) production of thin film based electronic devices (e.g. solar cells, activematrix TFT backplanes & touch screens) combine the advantages of the use of inexpensive, lightweight & flexible substrates with high throughput production. Significant cost reduction opportunities can also be found in terms of processing tool capital cost, utilized substrate area and process gas flow when compared with batch processing systems. Nevertheless, material handling, device patterning and yield issues have limited widespread utilization of R2R manufacturing within the electronics industry.

Technologies for pattern fabrication on a flexible substrate are being developed for various flexible devices. A patterning technique for a smaller pattern of the order of sub-100 nm will be needed in the near future. Roll-to-roll Nano-Imprint Lithography (RtR-NIL) is promising candidate for extremely low-cost fabrication of large-area devices in large volumes. We have tried to transfer sub-100 nm patterns, especially sub-30 nm patterns, onto ultraviolet (UV) curable resin on film substrate by RtR-NIL. We demonstrate a 24 nm pattern on a film substrate by RtR-NIL and the method's potential for sub-100 nm patterning.

Good surface quality of plastic substrates is essential to reduce pixel defects during roll-to-roll fabrication of flexible display active matrix backplanes. Standard polyimide substrates have a high density of "bumps" from fillers and belt marks and other defects from dust and surface scratching. Some of these defects could be the source of shunts in dielectrics. The gate dielectric must prevent shorts between the source/drain and the gate in the transistors, resist shorts in the hold capacitor and stop shorts in the data/gate line crossovers in active matrix backplanes fabricated by self-aligned imprint lithography (SAIL) roll-to-roll processes. Otherwise data and gate lines will become shorted creating line or pixel defects. In this paper, we discuss the development of a proprietary UV curable planarization material that can be coated by roll-to-roll processes. This material was engineered to have low shrinkage, excellent adhesion to polyimide, high dry etch resistance, and great chemical and thermal stability. Results from PECVD deposition of an amorphous silicon stack on the planarized polyimide and compatibility with roll-to-roll processes to fabricate active matrix backplanes are also discussed. The effect of the planarization on defects in the stack, shunts in the dielectric and curvature of finished arrays will also be described.

The ability to pattern materials at the nanoscale can enable a variety of applications ranging from high density data storage, displays, photonic devices and CMOS integrated circuits to emerging applications in the biomedical and energy sectors. These applications require varying levels of pattern control, short and long range order, and have varying cost tolerances. Extremely large area R2R manufacturing on flexible substrates is ubiquitous for applications such as paper and plastic processing. It combines the benefits of high speed and inexpensive substrates to deliver a commodity product at low cost. The challenge is to extend this approach to the realm of nanopatterning and realize similar benefits. The cost of manufacturing is typically driven by speed (or throughput), tool complexity, cost of consumables (materials used, mold or master cost, etc.), substrate cost, and the downstream processing required (annealing, deposition, etching, etc.). In order to achieve low cost nanopatterning, it is imperative to move towards high speed imprinting, less complex tools, near zero waste of consumables and low cost substrates. The Jet and Flash Imprint Lithography (J-FIL^TM) process uses drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for memory markets including Flash memory and patterned media for hard disk drives. In this paper we address the key challenges for roll based nanopatterning by introducing a novel concept: Ink Jet based Roll-to-Roll Nanopatterning. To address this challenge, we have introduced a J-FIL based demonstrator product, the LithoFlex 100. Topics that are discussed in the paper include tool design and process performance. In addition, we have used the LithoFlex 100 to fabricate high performance wire grid polarizers on flexible polycarbonate (PC) films. Transmission of better than 80% and extinction ratios on the order of 4500 have been achieved.

Directed self-assembly (DSA) of block copolymers (BCPs) is a promising technology for advanced patterning at future technology nodes, but significant hurdles remain for commercial implementation. The most widely studied material for DSA is poly(styrene-block-methyl methacrylate) (PS-PMMA), but this material has a relatively weak segregation strength that has limited its utility to patterns above 24 nm pitch. This paper reports on some of Dow's efforts to develop new materials capable of extending DSA to smaller pitch by development of new BCP copolymer materials with stronger segregation strength. Some preliminary efforts are reported on new substrate treatments that stabilize perpendicular orientations in a high-χ block copolymer that also incorporate an etch-resistant block to facilitate patterning at small dimensions. In addition, development of new block copolymer materials that have a χ-parameter that is large enough to drive defect reduction and but not so high that it precludes thermal annealing are also presented. DSA of these new materials is demonstrated using thermal annealing processes at pitch ranging from 40 to 16 nm, and etch capability is also demonstrated on a material with 18 nm pitch. These technologies hold promise for the extension of DSA to sub 24 nm pitch.

Theoretical methods are critical to our understanding of defect formation in block copolymer lithography processes. We have previously applied self-consistent field theory (SCFT) to study the energetics of dislocation and disclination defects prevalent in graphoepitaxy of "standing up" lamellae, and present results of a further refined approach accounting for polydispersity and polymer-substrate interactions. Broadening the scope of our investigation to include systems that deviate from the ideal monodisperse and neutral substrate conditions provides insight into how precisely these factors must be controlled to effectively suppress defects experimentally.

Directed self assembly (DSA) of block copolymers is an emerging technology for achieving sub-lithographic resolution. We investigate the directed self assembly of two systems, polystyrene-block-poly-DL-lactic acid (PS-b-PDLA) and PSb- poly(methyl methacrylate). For the PS-b-PDLA system we use an open source EUVL resist and a commerciallyavailable underlayer to prepare templates for DSA. We investigate the morphology of the phase separated domains and compare the LER of the resist and the PS-PDLA interface. For the PS-b-PMMA system we again use an open source resist, but the annealing conditions in this case require crosslinking of the resist prior to deposition of the block copolymer. For this system we also investigate the morphology of the phase separated domains and compare the LER of the resist and the PS-PMMA interface.

In this paper, we present the research progress made in maskless EUV lithography and discuss the emerging opportunities for this disruptive technology. It will be shown nanomirrors based maskless approach is one path to costeffective and defect-free EUV lithography, rather than making it even more complicated. The focus of our work is to optimize the existing vertical comb process and scale down the mirror size from several microns to sub-micron regime. The nanomirror device scaling, system configuration, and design issues will be addressed. We also report our theoretical and simulation study of reflective EUV nanomirror based imaging behavior. Dense line/space patterns are formed with an EUV nanomirror array by assigning a phase shift of π to neighboring nanomirrors. Our simulation results show that phase/intensity imbalance is an inherent characteristic of maskless EUV lithography while it only poses a manageable challenge to CD control and process window. The wafer scan and EUV laser jitter induced image blur phenomenon is discussed and a blurred imaging theory is constructed. This blur effect is found to degrade the image contrast at a level that mainly depends on the wafer scan speed.

A phase segregating polymer blend comprising a SOD precursor polysilazane and an organic polymer PSαMS [poly(styrene-co-α-methyl styrene)] was studied. By utilizing similar approaches employed in DSA (directed self-assembly) such as patterned substrates, surface chemical modification etc and their combination, we achieved 2xnm spacer and airgap-like structure. Vertical phase separation and cylinder microdomains in the film of this blend can be straightforwardly observed by cross-section SEM (Scanning Electron Microscope) respectively. The airgap-like structure derived from cylinder microdomains was directly obtained on ArF resist pattern. Spacer derived from vertical phase separation was obtained on pretreated ArF resist pattern.

Directed self-assembly (DSA) of block copolymers is a promising technique for producing sub-30 nm pitch regular patterns, and the development of these DSA techniques could benefit greatly from computer simulation of such methods. Current simulation methods such as mean field approaches suffer from a number of limitations that affect their accuracy and their level of detail. In this work a simulation approach based on the use of Protracted Colored Noise Dynamics (PCND) with coarse grained mesoscale polymer models based on statistical segment beads has been developed and studied. It has been shown that using PCND allows simulations to reach an equilibrium state at least 35 times faster than without PCND.

Nanoimprint Lithography and a mold, mold replication from an EB master mold as well, those are essential for a large-scale production of bit patterned media. 1Tbit/inch² (bit pitch 25nm) areal density on a 2.5inch HDD media, it is feasibility demonstration target all the media makers and the HDD makers are aiming at. This paper describes difficulties we faced, and solutions we established by designing and optimizing materials and process, to fabricate 25nm pitch master mold by EBL as well as working replica mold by NIL.

Lithography faces today many challenges to meet the ITRS road-map. 193nm is still today the only existing industrial option to address high volume production for the 22nm node. Nevertheless to achieve such a resolution, double exposure is mandatory for critical level patterning. EUV lithography is still challenged by the availability of high power source and mask defectivity and suffers from a high cost of ownership perspective. Its introduction is now not foreseen before 2015. Parallel to these mask-based technologies, maskless lithography regularly makes significant progress in terms of potential and maturity. The massively parallel e-beam solution appears as a real candidate for high volume manufacturing. Several industrial projects are under development, one in the US, with the KLA REBL project and two in Europe driven by IMS Nanofabrication (Austria) and MAPPER (The Netherlands). Among the developments to be performed to secure the takeoff of the multi-beam technology, the availability of a rapid and robust data treatment solution will be one of the major challenges. Within this data preparation flow, advanced proximity effect corrections must be implemented to address the 16nm node and below. This paper will detail this process and compare correction strategies in terms of robustness and accuracy. It will be based on results obtained using a MAPPER tool within the IMAGINE program driven by CEA-LETI, in Grenoble, France. All proximity effects corrections and the dithering step were performed using the software platform Inscale® from Aselta Nanographics. One important advantage of Inscale® is the ability to combine both model based dose and geometry adjustment to accurately pattern critical features. The paper will focus on the advantage of combining those two corrections at the 16nm node instead of using only geometry corrections. Thanks to the simulation capability of Inscale®, pattern fidelity and correction robustness will be evaluated and compared between the correction strategies. This work will be lead on the most critical layers of the 16nm integrate circuits layouts which are contact and metal 1. Finally the aim of this paper is to demonstrate that a complete data preparation flow including advanced proximity effects corrections, simulation and verification capabilities is available for the maskless lithography at the 16nm node and below, through the direct write version of Inscale®. This data preparation platform is already in use in several laboratories for direct write processes.

We present an analysis of the performance of an all electro-static electron-beam column designed for CEBL (Complementary Electron Beam Lithography). To meet the requirements of CEBL at advanced technology nodes (16 nm half-pitch and beyond), a beam size of < 20 nm FWHM (Full Width Half Maximum) and overlay accuracy of < 4 nm are needed. Beam current and beam energy must be optimized to achieve these specifications while meeting throughput requirements. In this paper, we present an in-depth analysis of the resolution of Multibeam's electron beam column as a function of beam energy. We focus on an analysis of beam energy below 30 keV, to avoid wafer heating and improve overlay accuracy. The beam size is analyzed with respect to aperture size and current. Spherical aberrations, chromatic aberrations and other effects at various beam energy levels are analyzed. At 7.5 or 5 keV beam energy, the 2 dominating factors in the beam spot size are the image size of the virtual source of the TFE (thermal field emitter) electron gun, chromatic and spherical aberrations. Performance of the column and process window to meet patterning requirements will be discussed.

Developers of e-beam lithography systems are pursuing diverse strategies to bolster throughput. To achieve parallelism, some e-beam efforts focus on building multiple-columns, and others focus on developing columns with multiple beamlets. In this paper, we discuss the benefits and throughput of a multiple column approach for a particular application: Complementary E-Beam Lithography (CEBL). CEBL is a novel approach where the e-beam lithography system is used only to pattern the smallest features. Everything else is patterned with existing optical lithography equipment. By working hand-in-hand with optical lithography, CEBL provides an urgently needed solution to create next-generation microchips. Moreover, CEBL is extendable for multiple technology generations. We show how a multiple column approach is the best way to meet the requirements for CEBL, including high throughput, high resolution and overlay accuracy, without excess complexity or cost.

While current and next generation lithographic techniques mostly focus on increasing resolution, line edge roughness (LER) remains one of the primary problems that limit the progress of scaling. In this paper, we examine the impact of lithographically induced line edge roughness on device performance using 3D TCAD (Technology CAD) simulation. We propose a methodology to reduce line edge roughness and examine the impact using simulation-based atomistic analysis of microscopic surface roughness. We show that several alternative wafer processing options - such as orientation dependent etching, selective epitaxy, and amorphization followed by solid phase epitaxial recrystallization - significantly reduce the lithography-induced line edge roughness. In particular, this is possible for the {111} silicon surfaces, due to their abnormally low etching and epitaxy rates compared to the other crystal orientations. For FinFETs and memory devices, this corresponds to non-standard (110) wafers with structures aligned across the <111> crystal direction. A detailed example is given on how the crystal self-assembly suppresses line edge roughness and cuts the average surface slope by a factor of four during a ten minute selective epitaxy process. The remaining surface roughness is limited to a few atomic steps and enables transistor scaling to the end of the roadmap.

In plasmonic nano lithography, a photoresist responds to the localized electric field which decays evanescently in the direction of depth. A simple analytic model is suggested to predict profiles of exposed and finally developed pattern with a finite contrast of photoresist. In this model, the developing process is revisited by accounting the variation of dissolution rate with respect to expose dose distribution. We introduce the concept of nominal developing thickness (NDT) to determine the optimized developing process fitting to the isointensity profile. Based on this model, we obtained three dimensional distribution of near-field of bowtie shaped plasmonic nano aperture in a metal film from the near-field lithography pattern profile. For the near-field exposure, we fabricated a nano aperture in a aluminum metal film which is coated on the contact probe tip. By illuminating 405 nm diode laser source, the positive type photoresist is exposed by the localized electric field produced by nano aperture. The exposed photoresist is developed by the TMAH based solution with a optimum NDT, which leads the developing march encounters the isoexposure contour at threshold dose. From the measurement of developed pattern profile with a atomic force microscope (AFM), the three-dimensional isoexposure (or iso-intensity) surface at the very near region from the exit plane of an aperture (depth: 5 ~ 50 nm) is profiled. Using the threshold dose of photoresist and exposure time, the absolute intensity level is also measured. The experimental results are quantitatively compared with the calculation of FDTD (finite- difference time-domain) method. Concerning with the error in exposure time and threshold dose value, the error in measurement of profile and intensity are less than 6% and 1%, respectively. We expect the lithography model described in this presentation allows more elaborated expectation of developed pattern profile. Furthermore, a methodology of mapping is useful for the quantitative analysis of near-field distribution of nano-scale optical devices.

We suggest a geometrically modified probe to achieve high positioning accuracy for plasmonic lithography which can record nanometer scale features and has high throughput. Instead of a cantilever probe, we propose a circular probe which has arc-shaped arms that hold the tip at the center. The modified probe is based on the fixed-fixed beam in material mechanics. To calculate the tip displacement, we used a finite element method (FEM) for a circular probe and compared the results with cantilever probe. We considered a silicon-based micro-fabrication process to design the probe. The probe has a square outline boundary with a length of 50μm, four arms, and a pyramidal tip with a height of 5μm. The ratio of the lateral tip displacement to the vertical deflection was evaluated to indicate the positioning accuracy. The probe has higher accuracy by a factor of 10³ and 10 in approach mode and scan mode, respectively, compared to a cantilever probe. We expect that a circular probe is appropriate for the applications that require high positioning accuracy, such as nanolithography with a contact probe and multiple-probe arrays.

We investigated a high-resolution chemically amplified resist for introducing a multi-column cell electron-beam directwriting system into the manufacturing of sub-14 nm technology node LSIs. The target of total blur, which leads to an exposure latitude above 10%, is less than 13.6 nm for 14 nm logic node LSIs. We divided the total blur into three terms, forward-scattering, electron-beam and resist. At a 40 nm-thick resist, the forward-scattering blur was calculated as 1.0 nm in lithography simulation, and beam blur was estimated to be 7.1 nm from the patterning results of hydrogen silsesquioxane. We found that there is a proportional relation between resist blur and acid diffusion length by using a new evaluation method that uses a water-soluble polymer. By applying a chemically amplified resist with a short acid diffusion length, resist blur decreased to 14.5 nm. Even though total blur is still 16.2 nm, we have already succeeded in resolving 20 nm line and space patterns at an exposure dose of 79.6 μC/cm².

Techniques to appropriately control the key factors for a character projection (CP) based electron beam direct writing (EBDW) technology for mass production are shown and discussed. In order to achieve accurate CD control, the CP technique using the master CP is adopted. Another CP technique, the Packed CP, is used to obtain suitable shot count. For the alignment on the some critical layers which have the normally an even surface, the alignment methodology differ from photolithography is required. The process that etches the SiO₂ material in the shallow trench isolation is added and then the alignment marks can be detected using electron beam even at the gate layer, which is normally on an even surface. The proximity effect correction using the simplified electron energy flux model and the hybrid exposure are used to obtain enough process margins. As a result, the sufficient CD accuracy, overlay accuracy, and yield are obtained on the 65 nm node device. The condition in our system is checked using self-diagnosis on a regular basis, and scheduled maintenances have been properly performed. Due to the proper system control, more than 10,000 production wafers have been successfully exposed so far without any major system downtime. It is shown that those techniques can be adapted to the 32 nm node production with slight modifications. For the 14 nm node and beyond, however, the drastic increment of the shot count becomes more of a concern. The Multi column cell (MCC) exposure method, the key concept of which is the parallelization of the electron beam columns with a CP, can overcome this concern. It is expected that by using the MCC exposure system, those techniques will be applicable to the rapid establishment for the 14 nm node technology.

Block co-polymer (BCP) lithography is becoming an established technique for patterning beyond optical lithography limitations. It is based on combining the intrinsic property of the block co-polymers to phase separate at the molecular scale with the capabilities of conventional top-down lithographic methods for patterning surfaces. Guiding the selfassembly of block co-polymers by surface chemical modification is one of the most used processes to drive the selfassembly in a convenient way. It consists on using lithography and oxygen plasma to create different wettability regions on a polymer brush grafted on the surface. For creating patterns with sub-22 nm resolution, this process introduces a tight restriction in the guiding lithography process. We present an easier guided self-assembly process by surface chemical modification that allows for a more relaxed guiding pattern specifications, providing a simpler route for the fabrication of nanometer scale structures.

We propose an advanced proximity effect correction method, in which all patterns of various sizes are written by character projection (CP) method, and the dose modulation and the auxiliary shot generation are performed using multiple area density maps with different mesh sizes according to the range of electron scatterings. We investigated the possibility that all patterns of various sizes could be written by using small number of CP characters of a single line with fixed width, which is called the "master-CP". We then estimated the range of the designed line width that can be supported by a master-CP and the number of master-CPs which are needed in order to support all patterns of various sizes. We found that only 5-7 master-CPs are required in terms of the dose margin, the rate of increase in the correction dose caused by using the master-CP of different width from the design pattern and the shot positioning error, and they have a low impact on the CP mask. Moreover, we estimated the effect of auxiliary shots on the throughput for 14 nm node technology. The percentage of auxiliary shots in the exposure time was less than 12.1%, even though a test pattern data was made by shrinking a 65 nm node logic LSI where the layout did not repeat very regularly. Therefore, as the layout becomes regularly-repeated to 14 nm node, the effect of the auxiliary shots would not be a dominant factor for the throughput.