21 March 2012 Addressing LER through atomistic self-assembly
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While current and next generation lithographic techniques mostly focus on increasing resolution, line edge roughness (LER) remains one of the primary problems that limit the progress of scaling. In this paper, we examine the impact of lithographically induced line edge roughness on device performance using 3D TCAD (Technology CAD) simulation. We propose a methodology to reduce line edge roughness and examine the impact using simulation-based atomistic analysis of microscopic surface roughness. We show that several alternative wafer processing options - such as orientation dependent etching, selective epitaxy, and amorphization followed by solid phase epitaxial recrystallization - significantly reduce the lithography-induced line edge roughness. In particular, this is possible for the {111} silicon surfaces, due to their abnormally low etching and epitaxy rates compared to the other crystal orientations. For FinFETs and memory devices, this corresponds to non-standard (110) wafers with structures aligned across the <111> crystal direction. A detailed example is given on how the crystal self-assembly suppresses line edge roughness and cuts the average surface slope by a factor of four during a ten minute selective epitaxy process. The remaining surface roughness is limited to a few atomic steps and enables transistor scaling to the end of the roadmap.
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Victor Moroz, Victor Moroz, Lars Bomholt, Lars Bomholt, } "Addressing LER through atomistic self-assembly", Proc. SPIE 8323, Alternative Lithographic Technologies IV, 83231Z (21 March 2012); doi: 10.1117/12.916231; https://doi.org/10.1117/12.916231


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