Transistor architecture impact on wafer inspection

Timothy F. Crimmins

doi:10.1117/12.917009

4 April 2012 Transistor architecture impact on wafer inspection

Timothy F. Crimmins

Proceedings Volume 8324, Metrology, Inspection, and Process Control for Microlithography XXVI; 83240C (2012) https://doi.org/10.1117/12.917009
Event: SPIE Advanced Lithography, 2012, San Jose, California, United States

Abstract

Pitch and CD scaling have been the main drivers of wafer inspection (WI) requirements, with tighter pitches and smaller CD's pushing the adoption of inspection tools with greater capabilities. With the introduction of strained silicon, Hi-k / metal gates and tri-gate transistors, integration schemes are playing a prominent role in WI. The present paper explores, through FDTD aerial image simulations, the impact of device integration scheme on WI. Various defect types are simulated for planar gate, planar Hi-k / metal gate and tri-gate transistors and the impact to WI requirements are explored.

Citation Download Citation

Timothy F. Crimmins "Transistor architecture impact on wafer inspection", Proc. SPIE 8324, Metrology, Inspection, and Process Control for Microlithography XXVI, 83240C (4 April 2012); https://doi.org/10.1117/12.917009

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available