Recess gate process control by using 3D SCD in 3xm vertical DRAM

Ming-Feng Kuo; Sheng-Hung Wu; Tien-Hung Lan; Shuang Hsun Chang; Elvis Wang; Houssam Chouaib; Harvey Cheng; Qiang Zhao

doi:10.1117/12.916143

3 April 2012 Recess gate process control by using 3D SCD in 3xm vertical DRAM

Ming-Feng Kuo, Sheng-Hung Wu, Tien-Hung Lan, Shuang Hsun Chang, Elvis Wang, Houssam Chouaib, Harvey Cheng, Qiang Zhao

Proceedings Volume 8324, Metrology, Inspection, and Process Control for Microlithography XXVI; 83241Z (2012) https://doi.org/10.1117/12.916143
Event: SPIE Advanced Lithography, 2012, San Jose, California, United States

Abstract

As DRAM design advances from planar to vertical integration, process control of the recessed gate, generated by etching after patterning in vertical DRAM, is very critical because of the impact on device electrical characteristics and subsequent effect on yield. 3D Scatterometry Critical Dimension (3D SCD) technology is a widely-used metrology approach for process control for leading edge CMOS and DRAM IC manufacturing. In this paper, the latest KLA-Tencor AcuShape^TM modeling software with 3D SCD capability is used in the modeling and solution development, and the SpectraShape^TM 8660 is used for data collection and CD measurement. Recess gate measurements were taken in the active cell area having a non-orthogonal structure. The SCD measurement results were successfully confirmed to correlate well with cross-section Scanning Electron Microscope (X-SEM) and electrical performance data.

Citation Download Citation

Ming-Feng Kuo, Sheng-Hung Wu, Tien-Hung Lan, Shuang Hsun Chang, Elvis Wang, Houssam Chouaib, Harvey Cheng, and Qiang Zhao "Recess gate process control by using 3D SCD in 3xm vertical DRAM", Proc. SPIE 8324, Metrology, Inspection, and Process Control for Microlithography XXVI, 83241Z (3 April 2012); https://doi.org/10.1117/12.916143

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