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5 April 2012 Accelerating litho technology development for advanced design node flash memory FEOL by next-generation wafer inspection and SEM review platforms
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Abstract
Development of an advanced design node for NAND flash memory devices in semiconductor manufacturing requires accelerated identification and characterization of yield-limiting defect types at critical front-end of line (FEOL) process steps. This enables a shorter development cycle time and a faster production ramp to meet market demand. This paper presents a methodology for detecting defects that have a substantial yield impact on a FEOL after-develop inspection (ADI) layer using an advanced broadband optical wafer defect inspector and a scanning electron microscope (SEM) review tool. In addition, this paper presents experimental data that demonstrates defect migration from an ADI layer to an after-clean inspection (ACI) layer, and provides clear differentiation between yield-impacting critical defects and noncritical defects on the layers. The goal of these studies is to determine the feasibility of implementing an inspection point at ADI. The advantage of capturing yield-limiting defects on an ADI layer is that wafers can be reworked when an excursion occurs, an option that is not always possible for ACI layers. Our investigation is divided into two parts: (1) Inspection of an ADI layer with high sensitivity to find an accurate representation of the defect population and to gain understanding on the propagation of defects from the ADI layer to the ACI layer; and, (2) Inspection of an ACI layer to develop an understanding of unique defects generated by the ACI process step. Overall, this paper discusses the advantages of baselining defectivity at ADI process levels for accelerated development of advanced design node memory devices.
© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Byoung Ho Lee, Jeongho Ahn, Dongchul Ihm, Soobok Chin, Dong-Ryul Lee, Seongchae Choi, Junbum Lee, Ho-Kyu Kang, Gangadharan Sivaraman, Tetsuya Yamamoto, Rahul Lakhawat, Ravikumar Sanapala, Chang Ho Lee, and Arun Lobo "Accelerating litho technology development for advanced design node flash memory FEOL by next-generation wafer inspection and SEM review platforms", Proc. SPIE 8324, Metrology, Inspection, and Process Control for Microlithography XXVI, 832429 (5 April 2012); https://doi.org/10.1117/12.916505
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