Abstract
As Extreme Ultra Violet technology (EUV) is being introduced, multilayer hard mask patterning becomes a key option
in order to transfer the lithographic patterns into the circuit stack. In particular, spin-on multilayers can play a decisive
role on the process roadmap as a more cost-effective solution than Chemical Vapour Deposition options. The integration
of spin-on hard masks in EUV technology nevertheless requires these products to be EUV-outgassing friendly. In
addition to this, the spin-on solutions must withstand the demanding photoresist and circuit stack aspect ratios during
patterning. This paper presents the EUV process development for contacted metal lines with 30nm half-pitch dimensions
in a dual damascene application. The performance of an all-spin-on multilayer system composed of an EUVphotosensitive
layer, an organic underlayer, a silicon-rich middle layer and a carbon-rich bottom layer is demonstrated.
Firstly, outgassing of the various polymer layers in vacuum is a critical parameter to control since it can directly impact
the EUV-tool-optics lifetime. The qualification, selection and process optimisation of different materials for use in the
ASML NXE:3100 EUV scanner are shown by interpreting Residual Gas Analysis data. The outgassed species for
different types of layers are compared. In this study, the shielding effect of the top layers on the outgassing of the layers
underneath is quantified. The influence of the layer composition is also discussed.
Secondly, the lithographic performance of the 30nm half-pitch process on the NXE:3100 is characterized with process
windows and profile control using the IMEC process-of-reference. The CD uniformity results within wafer and across
wafer-batches are used to demonstrate the process maturity.
Finally, considering the patternability of the EUV process, we demonstrate the ability of the all-spin-on multilayer
system to planarize over the challenging dual damascene topography. To conclude on the potential of this scheme, we
describe the etched dual damascene patterns into a dielectric stack which is representative for the 30nm half pitch
technology node.
