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20 March 2012 CD error budget analysis for self-aligned multiple patterning
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Abstract
EUV lithography is one of the most promising techniques for sub-20-nm half-pitch HVM devices, however it is well known that EUV lithography solutions still face significant challenges. Therefore we have focused on self-aligned double patterning (SADP), because SADP easily enables fine periodical patterning. As you know, SADP techniques have already been applied to HVM devices such as NAND Flash memory. These techniques will also be extended to DRAM and logic mass-production devices in the near future. In general, self-aligned multi-patterning consists of SADP, triple patterning (SATP), quadruple patterning (SAQP), etc. We have already introduced innovative resist core based SADP/SAQP techniques and have demonstrated results in past SPIE sessions.[1][2][3] Our proposed SiO2 spacer is directly deposited on a resist core by a low-temperature deposition process.SATP and SAQP enable further down-scaling to 10-15 nm hp from SADP levels, however the CD controllability for SATP/SAQP becomes more sensitive. In this paper, we will discuss CD error budget analysis for self-aligned multi-patterning, including a newly developed SATP scheme.
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Kenichi Oyama, Sakurako Natori, Shohei Yamauchi, Arisa Hara, and Hidetami Yaegashi "CD error budget analysis for self-aligned multiple patterning", Proc. SPIE 8325, Advances in Resist Materials and Processing Technology XXIX, 832517 (20 March 2012); https://doi.org/10.1117/12.916280
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