Self-aligned spacer Double Patterning (SADP) has been adopted in HVM of NAND FLASH memory device, because
SADP can fabricate fine periodical line pattern more easily than pitch-split type DP. Furthermore, SADP can mitigate
overlay accuracy such like pith-split type DP needed. The remarkable feature of SADP process is the adoption of a SiO2
film that can be deposited at extremely low temperatures for spacer formation. SADP and this deposition process also
produce wide applicability to density multiplication on hole pattern.
In our previous study, hole pattern fabrication below 40nmhp was examined. 30nm hp hole pattern was viable with
single 193-immersion exposure successfully with our newly developed process scheme named EKB, and ultimate
down-scaling on hole pattern, achieved to 20nm hp, was introduced utilizing cross-SADP.
In logic device manufacturing, pattern layout is getting to single directional, tabbed Gridded design rule (GDR) for the
mitigation of various lithographic issues. Although Self-aligned type DP for hole pattern can describe periodical layout,
it is really enabled for future simplified pattern layout.
In this paper, successful demonstration results would be introduced in process simplification, process extendibility, CD
controllability and further downward scaling.