13 March 2012 Overlay metrology for low-k1: challenges and solutions
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Proceedings Volume 8326, Optical Microlithography XXV; 832602 (2012); doi: 10.1117/12.916376
Event: SPIE Advanced Lithography, 2012, San Jose, California, United States
Abstract
Typical overlay metrology marks like Box-in-Box or Advanced-Imaging-Marks print surprisingly poor when exposed with extreme off-axis-illumination. This paper analyzes the root-cause for this behavior and establishes a method how to understand and predict the results of overlay metrology on resist. A simulation flow is presented which covers the lithographic exposure as well as the actual inspection of the resist profiles. This flow is then used to study the impact of scanner/process imperfections on the overlay measurements; both image-based and diffraction-based overlay metrology are covered. This helps to gain a deeper understanding of the critical parameters in the printing and inspection of overlay marks, and eventually develop and assess mark enhancement strategies for image-based overlay metrology such as chopping, or assess the benefit of diffraction-based overlay metrology. In parallel to the simulations, results of wafer exposures are presented which investigate various aspects of overlay metrology and validate our simulations.
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Jens Timo Neumann, Jongsu Lee, Kiho Yang, Byounghoon Lee, Taehyeong Lee, Jeongsu Park, Chang-moon Lim, Donggyu Yim, Sungki Park, Eric Janda, Kaustuve Bhattacharyya, Chan-ho Ryu, Young-Hong Min, Kiki Rhe, Bernd Geh, "Overlay metrology for low-k1: challenges and solutions", Proc. SPIE 8326, Optical Microlithography XXV, 832602 (13 March 2012); doi: 10.1117/12.916376; https://doi.org/10.1117/12.916376
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KEYWORDS
Overlay metrology

Diffraction

Data modeling

Diffraction gratings

Metrology

Lithography

Semiconducting wafers

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