13 March 2012 Overlay metrology for low-k1: challenges and solutions
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Typical overlay metrology marks like Box-in-Box or Advanced-Imaging-Marks print surprisingly poor when exposed with extreme off-axis-illumination. This paper analyzes the root-cause for this behavior and establishes a method how to understand and predict the results of overlay metrology on resist. A simulation flow is presented which covers the lithographic exposure as well as the actual inspection of the resist profiles. This flow is then used to study the impact of scanner/process imperfections on the overlay measurements; both image-based and diffraction-based overlay metrology are covered. This helps to gain a deeper understanding of the critical parameters in the printing and inspection of overlay marks, and eventually develop and assess mark enhancement strategies for image-based overlay metrology such as chopping, or assess the benefit of diffraction-based overlay metrology. In parallel to the simulations, results of wafer exposures are presented which investigate various aspects of overlay metrology and validate our simulations.
© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jens Timo Neumann, Jens Timo Neumann, Jongsu Lee, Jongsu Lee, Kiho Yang, Kiho Yang, Byounghoon Lee, Byounghoon Lee, Taehyeong Lee, Taehyeong Lee, Jeongsu Park, Jeongsu Park, Chang-moon Lim, Chang-moon Lim, Donggyu Yim, Donggyu Yim, Sungki Park, Sungki Park, Eric Janda, Eric Janda, Kaustuve Bhattacharyya, Kaustuve Bhattacharyya, Chan-ho Ryu, Chan-ho Ryu, Young-Hong Min, Young-Hong Min, Kiki Rhe, Kiki Rhe, Bernd Geh, Bernd Geh, } "Overlay metrology for low-k1: challenges and solutions", Proc. SPIE 8326, Optical Microlithography XXV, 832602 (13 March 2012); doi: 10.1117/12.916376; https://doi.org/10.1117/12.916376

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