13 March 2012 Extending the DRAM and FLASH memory technologies to 10nm and beyond
Author Affiliations +
Memory devices such as DRAM and NAND flash will continue to increase their capacity through scaling, which will extend to below the 10nm regime. From a device physics perspective, there are possible solutions for scaling below 10nm. However, the challenges of sub-10nm scaling will come from the productivity. In fact, major challenges for the realization of high density memory devices are lithography and vertical etching of high aspect ratio holes in DRAM and 3D flash memories. Here, status and the direction of DRAM and flash memory scaling technologies will be reviewed with a special focus on the extendibility from not only device physics but also productivity points of view.
© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Kinam Kim, U-In Chung, Youngwoo Park, Jooyoung Lee, Jeongho Yeo, Dongchan Kim, "Extending the DRAM and FLASH memory technologies to 10nm and beyond", Proc. SPIE 8326, Optical Microlithography XXV, 832605 (13 March 2012); doi: 10.1117/12.920053; https://doi.org/10.1117/12.920053


3D-ICs created using oblique processing
Proceedings of SPIE (March 21 2016)
Single-expose patterning development for EUV lithography
Proceedings of SPIE (March 24 2017)
Benchmarking study of EUV resists for NXE:3300B
Proceedings of SPIE (April 04 2016)
Cost modeling 22nm pitch patterning approaches
Proceedings of SPIE (March 20 2018)

Back to Top