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13 March 2012A full-chip 3D computational lithography framework
3D lithography simulations capable of modeling 3D effects in all lithographic processes are becoming critical in OPC
and verification applications as semiconductor feature sizes continue to shrink. These effects include mask topography,
resist profile and wafer topography. In this work we present an efficient computational framework for full-chip 3D
lithography simulations. Since fast modeling of mask topography effects has been studied for many years and is a
relatively mature area, we will only briefly review a full-chip 3D mask model, Tachyon M3D, to highlight the
importance and modeling requirements for accurate prediction of best focus variations among different device features
induced by mask topography. We will focus our discussions on a full-chip 3D resist model, Tachyon R3D, its derivation
and simplification from a full physical resist model. The resulting model form is fully compatible with the existing 2D
resist model with added capabilities for resist profile and top loss prediction. A benchmark against the full physical
model will be presented as well. We will also describe the development of a full-chip 3D wafer topography model,
Tachyon W3D, and the preliminary results against rigorous simulations.