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13 March 2012 Design compliance for spacer is dielectric (SID) patterning
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Self-Aligned Double Patterning (SADP) is a strong candidate for the lower-Metal layers of the 14 nm node. Compared to Litho-Etch-Litho-Etch (LELE) Double Patterning, SADP has lower LWR (line-width roughness), tighter line-end minimum spacing, and lower sensitivity to overlay errors. However, design for SADP is more restricted than for LELE. This work explores the design of layouts compatible with the Spacer Is Dielectric (SID) flavor of SADP. It is easy to find layouts that are LELE-compliant but not SID-compliant. One reason is that polygon stitching is not allowed in SID. Another is that certain drawn-space values are forbidden in SID. In this paper, we will write down some basic rules for SID-compliant design, and introduce some SID-printing artifacts that may be worrisome.
© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Gerard Luk-Pat, Alex Miloslavsky, Ben Painter, Li Lin, Peter De Bisschop, and Kevin Lucas "Design compliance for spacer is dielectric (SID) patterning", Proc. SPIE 8326, Optical Microlithography XXV, 83260D (13 March 2012);

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