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13 March 2012 Process requirements for pitch splitting LELE double patterning at advanced logic technology node
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As IC dimensions continue to shrink beyond the 22nm node, optical single exposure cannot sustain the resolution required and various double patterning techniques have become the main stream prior to the availability of EUV lithography. Among various kinds of double patterning techniques, positive splitting pitch lithography-etch-lithographyetch (LELE) double patterning is chosen for printing complex foundry circuit designs. Tighter circuit CD and process margin control in such positive splitting pitch LELE double patterning process becomes increasingly critical especially for topography issues induced by the 1st mask patterning with the 2nd mask exposure. In this paper, laser parameters, topography issues with the 2nd mask exposure, and SMO effects on CD performances are described in terms of the proximity CD portion of the scanner CD budget. Laser parameters, e.g. spectral shape and bandwidth, were input into the photolithography simulator, Prolith, to calculate their impacts on circuit CD variation. Mask-bias dependent lithographic performance was calculated and used to illustrate the importance of well-controlled laser performance parameters. Recommended laser bandwidth, mask bias and topography requirements are proposed, based on simulation results to ensure that the tight CD control (< 1nm) required for advanced technology node products can be achieved.
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R. C. Peng, I. H. Huang, H. H. Liu, H. J. Lee, John Lin, Arthur Lin, Allen Chang, Benjamin Szu-Min Lin, and Ivan Lalovic "Process requirements for pitch splitting LELE double patterning at advanced logic technology node", Proc. SPIE 8326, Optical Microlithography XXV, 83260X (13 March 2012);

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