13 March 2012 Integration of pattern matching into verification flows
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Abstract
The OPC verification problems tend to get more complicated in terms of coding complexity and TAT (turnaround time) increase as the gate length get smaller. A well known example of coding complexity is waivers (OPC verification errors that are priory known to be safe on silicon) detection and elimination. Potential locations for hot spots extraction as well could be a time consuming process if executed on full chips. And finally, OPC verification flows run time is sometimes even larger than OPC runs. In this work, we introduce the use of pattern matching as a potential solution for many verification flows problems. Pattern matching offers a great TAT advantage since it is a DRC based process, thus it is much faster than time consuming LITHO operations. Also, its capability to match geometries directly and operability on many layers simultaneously eliminates complex SVRF coding from our flows. Firstly, we will use the pattern matching in order not to run OPC verification on basic designs identified by the OPC engineer to be error free, which is a very useful technique especially in Memory designs and improves the run time. Then, it will be used to detect waivers, which is hard to code, while running verification flows and eliminate it from the output, and consequently the reviewer will not be distracted by it and concentrate on real errors. And finally, it will be used to detect hot spots in a separate very quick run before standard LITHO verification run which gives the designer/OPC engineer the opportunity to fix design/OPC issues without waiting for lengthy verification flows, and that in turns further improves TAT.
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Tamer Desouky, Tamer Desouky, Omnia Saeed, Omnia Saeed, } "Integration of pattern matching into verification flows", Proc. SPIE 8326, Optical Microlithography XXV, 83261X (13 March 2012); doi: 10.1117/12.915267; https://doi.org/10.1117/12.915267
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