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13 March 2012 RET and DFM techniques for sub 30nm
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Abstract
The resolution enhancement through lithography hardware (wavelength and Numerical Aperture) has come to a stop putting the burden on computational lithography to fill in the resulting gap between design and process until the arrival of EUV tools. New Computational Lithography techniques such as Optical Proximity Correction (OPC), Sub Resolution Assist Feature (SRAF), and Lithography Friendly Design (LFD) constitute a significant transformation of the design. These new Computational Lithography applications have become one of the most computationally demanding steps in the design process. Computing farms of hundreds and even thousands of CPUs are now routinely used to run these applications. The 28nm node presents many difficulties due to low k1 lithography whereas the 20nm requires double patterning solutions. In this paper we present a global view of enhanced RET and DFM techniques deployed to provide a robust 28nm node and prepare for 20nm. These techniques include advanced OPC manipulation through end user IP insertion into EDA software, optimized sub resolution assist features (SRAF) placement and pixilated OPC. These techniques are coupled with a fast litho print check, aka LFD, for 28nm P&R.
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E. Yesilada, J. Entradas, C. Gardin, J. N. Pena, A. Villaret, V. Farys, C. Beylier, F. Robert, S. Postnikov, A. M. Armeanu, C. Moyroud, F. Chaoui, F. Bernard Granger, and O. Toublan "RET and DFM techniques for sub 30nm", Proc. SPIE 8326, Optical Microlithography XXV, 83262H (13 March 2012); https://doi.org/10.1117/12.915825
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