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14 March 2012 Yield enhancement with DFM
Seung Weon Paek, Jae Hyun Kang, Naya Ha, Byung-Moo Kim, Dae-Hyun Jang, Junsu Jeon, DaeWook Kim, Kun Young Chung, Sung-eun Yu, Joo Hyun Park, SangMin Bae, DongSup Song, WooYoung Noh, YoungDuck Kim, HyunSeok Song, HungBok Choi, Kee Sup Kim, Kyu-Myung Choi, Woonhyuk Choi, JoongWon Jeon, JinWoo Lee, Ki-Su Kim, SeongHo Park, No-Young Chung, KangDuck Lee, YoungKi Hong, BongSeok Kim
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Proceedings Volume 8327, Design for Manufacturability through Design-Process Integration VI; 832704 (2012) https://doi.org/10.1117/12.920029
Event: SPIE Advanced Lithography, 2012, San Jose, California, United States
Abstract
A set of design for manufacturing (DFM) techniques have been developed and applied to 45nm, 32nm and 28nm logic process technologies. A noble technology combined a number of potential confliction of DFM techniques into a comprehensive solution. These techniques work in three phases for design optimization and one phase for silicon diagnostics. In the DFM prevention phase, foundation IP such as standard cells, IO, and memory and P&R tech file are optimized. In the DFM solution phase, which happens during ECO step, auto fixing of process weak patterns and advanced RC extraction are performed. In the DFM polishing phase, post-layout tuning is done to improve manufacturability. DFM analysis enables prioritization of random and systematic failures. The DFM technique presented in this paper has been silicon-proven with three successful tape-outs in Samsung 32nm processes; about 5% improvement in yield was achieved without any notable side effects. Visual inspection of silicon also confirmed the positive effect of the DFM techniques.
© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
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Seung Weon Paek, Jae Hyun Kang, Naya Ha, Byung-Moo Kim, Dae-Hyun Jang, Junsu Jeon, DaeWook Kim, Kun Young Chung, Sung-eun Yu, Joo Hyun Park, SangMin Bae, DongSup Song, WooYoung Noh, YoungDuck Kim, HyunSeok Song, HungBok Choi, Kee Sup Kim, Kyu-Myung Choi, Woonhyuk Choi, JoongWon Jeon, JinWoo Lee, Ki-Su Kim, SeongHo Park, No-Young Chung, KangDuck Lee, YoungKi Hong, and BongSeok Kim "Yield enhancement with DFM", Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 832704 (14 March 2012); https://doi.org/10.1117/12.920029
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KEYWORDS
Design for manufacturing
Silicon
Polishing
Optical proximity correction
Back end of line
Metals
Failure analysis
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