Variability in performance and power of 40nm and 28nm CMOS cells is highly dependent on the context in which the
cells are used. In this study, the effects of context on a number of clock tree cells from standard cell libraries have been
investigated. The study also demonstrated how the Litho Electrical Analyzer (LEA) tool from Cadence® is used to
analyze the context-dependent variability. During the study, it was observed that the device characteristics including Vth,
Idsat, and Ioff are significantly affected by Layout Dependent Effects (LDE), resulting in variability of performance and
power of standard cells. Moreover, the dummy diffusions acting as mitigation process offered limited improvement for
the effects of context. On the other hand, the cell level variability due to stress was analyzed. So, it is suggested that the
relative variability of a cell is determined by its size and structure, and the variability can be improved to some extent by
editing the cells' structure.
Based on the analysis of the physical sources and properties of LDE, this paper presents a set of layout guidelines for
mitigating layout dependent variability of 40 and 28nm CMOS cells.