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14 March 2012 Analysis, quantification, and mitigation of electrical variability due to layout dependent effects in SOC designs
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Variability in performance and power of 40nm and 28nm CMOS cells is highly dependent on the context in which the cells are used. In this study, the effects of context on a number of clock tree cells from standard cell libraries have been investigated. The study also demonstrated how the Litho Electrical Analyzer (LEA) tool from Cadence® is used to analyze the context-dependent variability. During the study, it was observed that the device characteristics including Vth, Idsat, and Ioff are significantly affected by Layout Dependent Effects (LDE), resulting in variability of performance and power of standard cells. Moreover, the dummy diffusions acting as mitigation process offered limited improvement for the effects of context. On the other hand, the cell level variability due to stress was analyzed. So, it is suggested that the relative variability of a cell is determined by its size and structure, and the variability can be improved to some extent by editing the cells' structure. Based on the analysis of the physical sources and properties of LDE, this paper presents a set of layout guidelines for mitigating layout dependent variability of 40 and 28nm CMOS cells.
© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Yangang Wang, Mark Zwolinski, Andrew Appleby, Mark Scoones, Sonia Caldwell, Touqeer Azam, Philippe Hurat, and Chris Pitchford "Analysis, quantification, and mitigation of electrical variability due to layout dependent effects in SOC designs", Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 83270F (14 March 2012);


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