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14 March 2012 Variability aware compact model characterization for statistical circuit design optimization
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Variability modeling at the compact transistor model level can enable statistically optimized designs in view of limitations imposed by the fabrication technology. In this work we propose an efficient variabilityaware compact model characterization methodology based on the linear propagation of variance. Hierarchical spatial variability patterns of selected compact model parameters are directly calculated from transistor array test structures. This methodology has been implemented and tested using transistor I-V measurements and the EKV-EPFL compact model. Calculation results compare well to full-wafer direct model parameter extractions. Further studies are done on the proper selection of both compact model parameters and electrical measurement metrics used in the method.
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Ying Qiao, Kun Qian, and Costas J. Spanos "Variability aware compact model characterization for statistical circuit design optimization", Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 83270J (14 March 2012);

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