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14 March 2012 The complexity of fill at 28nm and beyond
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The history of dummy fill in semiconductor design goes back many generations of technology development. From its start with planarization requirements, fill needs have expanded across many wafer process manufacturing steps. They include lithography, etch, deposition, surface anneal, and device performance with stress analysis. Modern EDA tools have advanced to automatically place dummy shapes to meet these new requirements. These include placing multi-layer cell constructs, and multi-layer analysis during placement. New fill requirements have affected downstream flows such as extraction and timing analysis, physical verification, and RET flows. Further enhancements to fill tools and flows are under development to meet the total DFM needs for the next generations of chips.
© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Norma Rodriguez, Jie Yang, Bill Graupp, Jeff Wilson, and Eugene Anikin "The complexity of fill at 28nm and beyond", Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 83270Q (14 March 2012);

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