14 March 2012 Clean pattern matching for full chip verification
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Abstract
Layout verification is essential in the cutting-edge generation. Generally, it uses a lithography simulation (Lithography Compliance Check: LCC) and requires a lot of calculation time. In order to reduce LCC time, we propose a clean pattern matching method by means of a "clean pattern library". The proposed method searches for patterns without hotspots (clean patterns) which usually occupy the most of the chip area. The conventional hotspot pattern matching method has no guarantee that unmatched area is hotspot-free, so LCC is usually applied to the unmatched area. On the other hand, the proposed matching method searches for "clean" patterns so that most of the area need not to be verified. As a result, LCC time can be reduced. This paper shows the detailed flow of the proposed matching method. We present the experimental results of layout verification in our 40nm system LSI designs and the effectiveness of the proposed method is confirmed.
© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Satomi Nakamura, Satomi Nakamura, Tetsuaki Matsunawa, Tetsuaki Matsunawa, Chikaaki Kodama, Chikaaki Kodama, Takanori Urakami, Takanori Urakami, Nozomu Furuta, Nozomu Furuta, Shunsuke Kagaya, Shunsuke Kagaya, Shigeki Nojima, Shigeki Nojima, Shinji Miyamoto, Shinji Miyamoto, } "Clean pattern matching for full chip verification", Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 83270T (14 March 2012); doi: 10.1117/12.916316; https://doi.org/10.1117/12.916316
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