14 March 2012 A study of pattern variability for device performance
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As semiconductor process technology scales down to sub 30nm process node and beyond dimensions, the printability and process window of the lithographic patterns are seriously reduced due to the fundamental limit of the lithography and process variations. In this paper, we introduce a various analysis methodology of pattern variability for higher device performance using with applications of DBV (Design Based Verification). Pattern variability is affected by both pattern process margins and electrical margins such as distribution of gate length. Even if post lithography verification would carry out after model based OPC, Pattern variability is increased not only unpredictable OPC hotspots but also unanticipated hotspots by AEI loading skew in full-chip. Secondly, electrical hotspots which are extracted by tail distributions of gate length are not always reliable enough to represent critical path with gate length of full-chip. We constructed New OCV extraction flow with a full-chip pattern classification that is required for both gate distribution accuracy and analysis of gate tail patterns. In this report, we investigated about the relationship between a pattern feature and pattern distribution of transistor length.
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Tae-Heon Kim, Tae-Heon Kim, Dae-Han Han, Dae-Han Han, Ae-Ran Hong, Ae-Ran Hong, Yong-Hyeon Kim, Yong-Hyeon Kim, Joo-Sung Lee, Joo-Sung Lee, Yun-Hye Chu, Yun-Hye Chu, Kweon-Jae Lee, Kweon-Jae Lee, Yong-Jik Park, Yong-Jik Park, "A study of pattern variability for device performance", Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 83270Y (14 March 2012); doi: 10.1117/12.915934; https://doi.org/10.1117/12.915934

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