With the decrease of semiconductor device dimensions, line width roughness (LWR) becomes a challenging parameter
that needs to be controlled below 2nm in order to ensure good electrical performances of CMOS devices of the future
technological nodes. One issue is the significant LWR of the photoresist patterns printed by 193nm lithography that is
known to be partially transferred into the gate stack during the subsequent plasma etching steps. This issue could be
partially resolved by applying plasma pre treatment on photoresist before plasma transfer. Another issue is linked to the
noise level of the metrology tool, that causes a non negligible bias from true LWR values. Recently we proposed an
experimental protocol combining CD-SEM measurements and Power Spectral Density (PSD) fitting method for an
accurate estimation of the CDSEM noise level and extraction of unbiased LWR.
In this article, we use the developed CDSEM protocol to extract roughness parameters (true LWR, correlation length,
fractal exponent) of dense and isolated photoresist patterns exposed to various plasma treatments (HBr, H2, He, Ar), and
also to follow the evolution of the LWR during the subsequent plasma etching steps involved in gate patterning. We
show that the resist LWR is less improved in isolated than in dense lines with HBr plasma treatment because of carbon
species redeposition more important on isolated resist pattern sidewalls. Plasmas such as H2 that limit carbon
redeposition are more efficient to decrease significantly resist LWR in both dense and isolated lines. In addition we show
that all frequency roughness components are not equally transferred during gate patterning, and more particularly that the
high frequency roughness components are lost.