8 June 2012 The simulation on diode-clamped five-level converters common-mode voltage suppression with zero-vector PWM strategy
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Proceedings Volume 8334, Fourth International Conference on Digital Image Processing (ICDIP 2012); 83343Z (2012) https://doi.org/10.1117/12.968555
Event: Fourth International Conference on Digital Image Processing (ICDIP 2012), 2012, Kuala Lumpur, Malaysia
Abstract
More and more researchers have great concern on the issue of Common-mode voltage (CMV) in high voltage large power converter. A novel common-mode voltage suppression scheme based on zero-vector PWM strategy (ZVPWM) is present in this paper. Taking a diode-clamped five-level converter as example, the principle of zero vector PWM common-mode voltage (ZCMVPWM) suppression method is studied in detail. ZCMVPWM suppression strategy is including four important parts, which are locating the sector of reference voltage vector, locating the small triangular sub-sector of reference voltage vector, reference vector synthesis, and calculating the operating time of vector. The principles of four important pars are illustrated in detail and the corresponding MATLAB models are established. System simulation and experimental results are provided. It gives some consultation value for the development and research of multi-level converters.
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Yonggao Zhang, Yonggao Zhang, Yanli Gao, Yanli Gao, Lizhong Long, Lizhong Long, } "The simulation on diode-clamped five-level converters common-mode voltage suppression with zero-vector PWM strategy", Proc. SPIE 8334, Fourth International Conference on Digital Image Processing (ICDIP 2012), 83343Z (8 June 2012); doi: 10.1117/12.968555; https://doi.org/10.1117/12.968555
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