13 January 2012 NBTI aware HLS using latches
Author Affiliations +
Time dependent performance degradation due to negative bias thermal instability (NBTI) is one of the most important reliability concerns for deep nano scale regime VLSI circuits. Under worst case NBTI can degrade circuit performance in terms of timing by more than 10% over a period of 3 years. Reliability decisions taken early in system design can bring significant benefits in terms of design quality. The proposed approach deals with use of latches and NBTI aware scheduling of DFG to overcome the timing violations caused by NBTI. The experimental results suggest that it incurs a very low area overhead and no performance penalty. We propose an algorithm to schedule the DFG and show results for some of the common filters like EW and AR.
© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Ramrakesh Jangir, Ramrakesh Jangir, Kalyan Singh Yadav, Kalyan Singh Yadav, } "NBTI aware HLS using latches", Proc. SPIE 8349, Fourth International Conference on Machine Vision (ICMV 2011): Machine Vision, Image Processing, and Pattern Analysis, 83493M (13 January 2012); doi: 10.1117/12.923771; https://doi.org/10.1117/12.923771


Diamond multichip modules
Proceedings of SPIE (November 30 1991)
Are we there yet? Looking beyond the end of scaling...
Proceedings of SPIE (April 28 2003)
Arithmetic processor design for the T9000 transputer
Proceedings of SPIE (November 30 1991)

Back to Top