13 January 2012 Hardware architecture of OFCE-HS for hardware implementation
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Proceedings Volume 8350, Fourth International Conference on Machine Vision (ICMV 2011): Computer Vision and Image Analysis; Pattern Recognition and Basic Technologies; 835007 (2012); doi: 10.1117/12.920137
Event: Fourth International Conference on Machine Vision (ICMV 11), 2011, Singapore, Singapore
Abstract
Optical flow algorithm proposed by Horn and Schunck (OFCE-HS) in 1981 was the first technique and one of the best performers for motion estimation. Attempts to implement OFCE-HS into real-time hardware have been performed by researchers. Hardware architecture of OFCE-HS proposed by Martin et al. with full integer for all calculations is one of the attempts. However, the hardware architecture has a significant drawback because it requires two dividers which decrease the speed of the system, increase the use of resources and add errors in the truncation of the least significant bits. To overcome this problem, new proposed hardware architecture of OFCE-HS is presented in this paper. With calculations using a combination of integer and fractional arithmetic, it is possible to reduce the number of dividers and to improve its performance. The goal of this work is to design hardware architecture of OFCE-HS which can increase the speed of the system, lower resource utilization and achieve good precision and accuracy compared previous works.
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Ruzali Rustam, Nor Hisham Hamid, Fawnizu Azmadi Hussin, "Hardware architecture of OFCE-HS for hardware implementation", Proc. SPIE 8350, Fourth International Conference on Machine Vision (ICMV 2011): Computer Vision and Image Analysis; Pattern Recognition and Basic Technologies, 835007 (13 January 2012); doi: 10.1117/12.920137; https://doi.org/10.1117/12.920137
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KEYWORDS
Machine vision

Optical flow

Motion estimation

Digital signal processing

Computer vision technology

Logic

Computer architecture

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