13 January 2012 An improved high-speed canny edge detection algorithm and its implementation on FPGA
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Edge is an important feature of image and it is very useful in machine vision application. In view of the parallelism, logic operation and pipelined of Field Programmable Logic Array (FPGA), this paper proposes an improved edge detection algorithm based on the Canny operator for FPGA. Median Filter in 3-way Parallel can complete image preprocessing in high-speed. Second Harmonic of the Variable Parameters (SHOVP) calculates the gradient easily and flexibly. 45 Degrees into the Direction of Gradient, and Non Maximum Suppression based on Quarter of the Gradient Direction will be completed easily just using logic operation. This algorithm transforms the complex data operation into multi-task operation, and simplifies arithmetic into logic operation. It improves the computing feasibility, effectiveness and real-time for FPGA. This paper gives the result of the algorithm based on FPGA.
© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Fangxin Peng, Fangxin Peng, Xiaofeng Lu, Xiaofeng Lu, Hengli Lu, Hengli Lu, Sumin Shen, Sumin Shen, } "An improved high-speed canny edge detection algorithm and its implementation on FPGA", Proc. SPIE 8350, Fourth International Conference on Machine Vision (ICMV 2011): Computer Vision and Image Analysis; Pattern Recognition and Basic Technologies, 83501V (13 January 2012); doi: 10.1117/12.920950; https://doi.org/10.1117/12.920950


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