The hybrid optical proximity correction (OPC) verification flow uses both compact and rigorous lithography
models. This is the approach we are investigating to meet the challenges to improve the accuracy while keeping the
turnaround time (TAT) in check for each new technology node.
The compact lithography model is derived from the Hopkins method to calculate the image at the wafer. They
consist of the pre-calculated optical kernel set that includes properties of projection, source optics, and the resist
effects. The image at the wafer is formed by the convolution of optical kernel set with the mask transmission. The
compact model is used for OPC and lithography rule checking (LRC) due to its excellent TAT in full chip
applications. Leading edge technology nodes, however, are inherently more sensitive to process variation and
typically contain more low contrast areas, sometimes resulting in marginal hotspots. In these localized areas, it is
desirable to have access to more predictive first principle lithography simulation. The Abbe method for lithography
simulation includes full 3D resist models which solve from the first principles (the reaction/diffusion equation of the
post exposure bake) to provide the highest accuracy. These rigorous models have the ability to provide added
insight into the 3D developed profile in resist at the wafer level to assist in the application of OPC, verification and
disposition of hotspots found by LRC using compact models.
The hybrid OPC verification takes the advantage of compact model for TAT and rigorous model for 3D profile
accuracy , . And since the rigorous lithography simulator already supports new technologies like double pattern
technology (DPT), electron beam (E-beam)  and extreme ultraviolet lithography (EUV)  this approach is
extendable to multiple technology nodes.